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Introduction to stm32-part2
- 7. A Glance at STM32 Amr Ali Abdel-Naby@2011 Introduction to STM32
- 8. Performance and Access Lines Amr Ali Abdel-Naby@2011 Introduction to STM32
- 10. Memory Mapping and Boot Modes Amr Ali Abdel-Naby@2011 Introduction to STM32
- 12. Clocking Configurations Amr Ali Abdel-Naby@2011 Introduction to STM32
- 17. GPIO Configuration Modes Amr Ali Abdel-Naby@2011 Introduction to STM32
- 20. EXTI Configuration Amr Ali Abdel-Naby@2011 Introduction to STM32
- 21. Analog to Digital Converter Amr Ali Abdel-Naby@2011 Introduction to STM32
- 22. Modes of Operation Amr Ali Abdel-Naby@2011 Introduction to STM32
- 23. Dual Conversion Modes Amr Ali Abdel-Naby@2011 Introduction to STM32
- 24. Simultaneous Modes Amr Ali Abdel-Naby@2011 Introduction to STM32
- 25. Combined Mode Amr Ali Abdel-Naby@2011 Introduction to STM32
- 26. Interleaved Modes Amr Ali Abdel-Naby@2011 Introduction to STM32
- 27. Alternate Trigger Mode Amr Ali Abdel-Naby@2011 Introduction to STM32
- 28. Combined Regular Simultaneous/Alternate Trigger Mode Amr Ali Abdel-Naby@2011 Introduction to STM32
- 29. Combined Injected Simultaneous/Alternate Trigger Mode Amr Ali Abdel-Naby@2011 Introduction to STM32
- 37. USART Example Usages Amr Ali Abdel-Naby@2011 Introduction to STM32
- 47. Multiple Reset Sources Amr Ali Abdel-Naby@2011 Introduction to STM32
- 48. Power Voltage Detect Amr Ali Abdel-Naby@2011 Introduction to STM32
- 49. Clock Security System Amr Ali Abdel-Naby@2011 Introduction to STM32
- 50. Watchdog Timers Amr Ali Abdel-Naby@2011 Introduction to STM32
Editor's Notes
- * 07/16/96 * ##
- STM32 has 2 lines; the performance line at the left and the access line at the right * 07/16/96 * ##
- Boot modes: User flash: Programmed with user application code System memory: Programmed in factory with boot code. Used when we program the user flash with our code SRAM: Used during development for faster download and booting * 07/16/96 * ##
- Clock Security System (CSS) used to back up in case of HSE failure to run the HSE instead. * 07/16/96 * ##
- The reset and clock control unit controls the clock tree bus bridges and backup domain. Configure the PLL Configure the buses * 07/16/96 * ##
- 12-bit resolution 18 channels: 16 external and 2 internal 1 MHZ sample rate Conversion time programmable An injected group conversion interrupts regular group conversions Analog watchdog ADC is used to detect over/under voltage conditions on any of the input channels Results are left-aligned or right-aligned An offset is deducted from the injected results Injected group results are sign extended DMA can be used to automate data transfer of results of ADC1 * 07/16/96 * ##
- * 07/16/96 * ##
- Extends the modes of operation of the ADC by HW SW implementation would be more complex! Adds 8 more modes of operations * 07/16/96 * ##