2. The Acorn RISC Machine
• First ARM was developed at Acorn Computers Limited, of
Cambridge, England between October 1983 and April 1985
• Before 1990, ARM stood for Acorn RISC Machine
• Later on ARM stands for Advanced RISC Machine
• RISC concept was introduced in 1980 at Stanford and Berkley
• ARM core limited founded in 1990
• ARM cores
-Licensed partners to develop and fabricate new
microcontrollers
-Soft core
3. The Acorn RISC Machine
• 16-bit CISC microprocessor had certain disadvantages
available in 1983
-They were slower than standard memory parts
-Instructions that took many clock cycles to complete
-Long interrupt latency
4. The ARM Architecture Inheritance
• The ARM chip was designed based on Berkeley RISC I and II
and the Stanford MIPS (Microprocessor without Interlocking
Pipeline Stages)
• Features Used from Berkeley RISC design
-a load-store architecture
-fixed length 32-bit instructions
-3-address instruction formats
• Features Rejected
-Register windows
-Delayed Branches
- Single Cycle execution of all instructions
5. The ARM Architecture Inheritance
• Based upon RISC Architecture with enhancements to meet
requirements of embedded applications
– A Large uniform register file
– Load-store architecture
– Uniform and fixed length instructions
– 32-bit processor
– Instructions are 32-bit long
– Good speed/power consumption ratio
– High Code Density
6. The Enhancement to Basic RISC Pro
• Control over ALU and shifter for every data processing
operations to maximize their usage
• Auto-Increment and auto-Decrement addressing modes to
optimize program loops
• Load and Store Multiple instructions to maximize data
throughput
• Conditional Execution of instruction to maximize execution
throughput
7. The ARM Architecture
multiply
data out register
instruction
decode
&
control
incrementer
register
bank
address register
barrel
shif ter
A[31:0]
D[31:0]
data in register
ALU
control
P
C
PC
A
L
U
b
u
s
A
b
u
s
B
b
u
s
register
8. Overview: Core data path
• Data items are placed in register file
-No data processing instructions directly manipulate data in
memory
• Instructions typically use two source registers and single result
or destinations registers
• A Barrel shifter on the data path can preprocess data before it
enters ALU
• Increment/Decrement logic can update register content for
sequential access independent of ALU
9. Registers
• General Purpose Registers hold either data or address
• All registers are of 32 bits
• Total 37 registers
• In user mode 16 data registers and 2 status registers are
visible
• Data registers: r0 to 15
-Three registers r13, r14, r15 perform special functions
-r13: stack pointer
-r14: link register (where return address is put whenever a
subroutine is called)
-r15: program counter
10. Registers
• Depending upon context, registers r13 and r14 can also be
used as GPR
• Any instruction which use r0 can as well be used with any
other GPR (r1-r13)
• In addition, there are two status registers
-CPSR: Current Program Status Register
-SPSR: Saved Program Status Register
11. ARM Programming Model
r13_und
r14_undr14_irq
r13_irq
SPSR_und
r14_abtr14_svc
user mode
fiq
mode
svc
mode
abort
mode
irq
mode
undefined
mode
usable in user mode
system modes only
r13_abt
r13_svc
r8_fiq
r9_fiq
r10_fiq
r11_fiq
SPSR_irqSPSR_abt
SPSR_svcSPSR_fiqCPSR
r14_fiq
r13_fiq
r12_fiq
r0
r1
r2
r3
r4
r5
r6
r7
r8
r9
r10
r11
r12
r13
r14
r15 (PC)
12. 12
Current Program Status Register
N: Negative results from ALU
Z: Zero result from ALU
C: ALU operation Carried out
V: ALU operation oVerflow
ARM CPSR format
Monitors and control Internal operations
N Z C V unused mode
31 28 27 8 7 6 5 4 0
IF T
13. 13
Current Program Status Register
• Sticky overflow flag – Q flag
-architecture 5TE only
-indicates if saturation has occurred during certain
operations
• Interrupt Disable Bits
-I = 1, disables the IRQ
-F = 1, disables the FIQ
N Z C V unused mode
31 28 27 8 7 6 5 4 0
IF T
14. 14
Current Program Status Register
• T Bit
-architecture xT only
-T = 0, processor in ARM state
-T = 1, processor in Thumb state
• Mode bits
-specify the processor mode
N Z C V unused mode
31 28 27 8 7 6 5 4 0
IF T
15. 15
Memory Organization
half-w ord4
w ord16
0123
4567
891011
byte0
byte
12131415
16171819
20212223
byte1byte2
half-w ord14
byte3
byte6
address
bit 31 bit 0
half-w ord12
w ord8
• Little Endian Form
• Address bus: 32 – bits
• 1 word = 32 – bits
• Memory (Byte-wide)
• Addresses decrease from
top to bottom and left to
right
• 32-bit word aligned for 8
and 16-bit words also
16. Load-Store Architecture
• Instruction set will only process values which are in registers
• The only operations which apply to memory state are ones
which copy memory values into registers(load instructions) or
copy register values into memory(store instruction)
• ARM does not support such ‘memory-to-memory’ operations
• Therefore all ARM instructions fall into three categories;
• 1) Data Processing Instructions
• 2) Data Transfer Instructions
• 3) Control Flow Instructions
17. The ARM instruction set
• The Load-Store Architecture
• 3-address data processing instructions
• Conditional execution of every instruction
• The inclusion of very powerful load and store multiple register
instructions
• The ability to perform a general shift operation and a general
ALU operation in a single instruction that executes in a single
clock cycle
• Open instruction set extension through the coprocessor inst
• A very dense 16-bit compressed instruction set in Thumb
mode
18. The I/O System
• ARM handles peripherals as “memory mapped devices with
interrupt support”.
• Interrupts:
IRQ: normal interrupt
FIQ: fast interrupt
Both are Level Sensitive and Maskable
• Normally most interrupt sources share the IRQ input
• Some may include DMA hardware external to the processor
to handle high-bandwidth I/O traffic
19. ARM exceptions
• Exceptions:
– Interrupts
– Supervisor Call
– Traps
• When an exception takes place:
– The value of PC is copied to r14_exc
– The operating mode changes into the respective exception
mode.
– The PC takes the exception handler vector address 0016 to
1C16
21. ARM development tools
• C or Assembler source files are compiled or assembled into
ARM object format (.aof) files
• Then linked into ARM image format (.aif) files
• The image format files can be built to include the debug
tables required by the ARM symbolic debugger (ARMsd)
which can load, run and debug programs either on hardware
such as the ARM Development Board or using a software
emulation of the ARM (the ARMulator)
• The ARMulator has been designed to allow easy extension of
the software model to include system features such as caches,
memory timing characteristics, and so on
22. The ARM C Compiler and
assembler
• ARM C compiler is compliant with the ANSI standard for C
• Uses ARM procedure Call Standard for all externally available
functions
• Can produce assembly source output instead of ARM object
format, so code can be inspected, or even hand optimized,
and then assembled subsequently
• Compiler can also produce Thumb code
• The ARM assembler Full macro assembler which produces
ARM object format output that can be linked with output
from the C compiler
• Nearer to Machine-level, with most assembly instructions
translating into single ARM (or Thumb) instructions.
23. The ARM Linker
• Takes one or more object files and combines them into an
executable program
• Resolves symbolic references between the object files and
extracts object modules from libraries as needed by the
program
• Can assemble the various components of the program in a
number of different ways, depending on weather the code is
to run in RAM or ROM, whether overlays are required, and so
on
• Linker includes debug tables in the output file
• Can also produce object library modules that are not
executable but are ready for efficient linking with object files
in future.
24. The ARMsd
• Front-end interface to assist in debugging programs running
either under emulation or remotely on a target system such
as the ARM development board
• Allows an executable program to be loaded into the
ARMulator or a development board and run
• Allows the setting of breakpoints, which are addresses in the
code that, if executed, cause execution to halt so that the
processor state can be examined
• In the ARMulator, or when running on hardware with
appropriate support, it also allows the setting of watchpoints
• Supports full source level debugging, allowing the C
programmer to debug a program using source file to specify
breakpoints and using variable names from original program
25. The ARMulator
• ARM emulator is a suite of programs that models the
behavior of various ARM processor cores in software on a
host system
• Can operate at various levels of accuracy:
• Instruction-accurate modeling gives the exact behavior of the
system state without regard to the precise timing
characteristics of the processor
• Cycle-accurate modeling gives the exact behavior of the
processor on a cycle-by-cycle basis, allowing the exact
number of clock cycles that a program requires to be
established
• Timing-accurate modeling presents signals at the correct time
within a cycle, allowing logic delays to be accounted for
26. The ARM Development Board
• ARM Development Board is a circuit board incorporating a
range of components and interfaces to support the
development of ARM-based systems
• Software Toolkit
• ARM Project Manager is a graphical front-end for the tools
• It supports the building of a single library or executable
image from a list of files that make up a particular project
• Source files (C, assembler, and so on)
• Object files
• Library files
• The source files may be edited within the Project Manager
• There are many options which may be chosen for the build
27. The ARM Software Toolkit
• Whether the output should be optimized for code size or
execution time
• Whether the output should be in debug or release form
• Which ARM processor is the target and particularly whether it
supports the Thumb instruction set
• JumpStart
• JumpStart tools from VLSI Technology, Inc., include the same
basic set of development tools but present a full X-windows
interface on a suitable workstation rather than the command-
line interface of the standard ARM toolkit
• There are many other suppliers of tools that support ARM
development
