Using MDE for the Formal Verification of Embedded Systems Modeled by UML Sequence Diagrams
1. Using MDE for the Formal
Verification of Embedded
Systems Modeled by UML
Sequence Diagrams
Francisco A. M. Nascimento
Marcio F. S. Oliveira
Flávio R. Wagner
SBCCI 2009 Natal, RN
2. Motivation
To cope with the growing complexity
of embedded systems design
Higher levels of abstraction
Exhaustive test of all possible
system executions is an impractical
or even impossible task
• Formal verification methods and
tools as a promising approach
3. Summary
• Model Driven Engineering (MDE)
• MDE-based Formal Verification
• Internal Application Metamodel – IAM
• LTA Metamodel - LTA
• Transforming UML into IAM+LTA
• Case Study
• Conclusion and Future Work
4. Model Driven Engineering
• Main artifacts to be constructed and
maintained are models
• Languages used to express models
are defined by means of meta-
models
• Software development consists of
transforming a model into another
one until a final model is obtained
that is ready to be executed
6. UML model
• Class diagrams (CD)
– Application components
– Hierarchy and modularity
– Structure
• Sequence diagrams (SD)
– Possible executions of the application
– A root SD specifies how the executions
are composed
– Behavior
19. Transforming UML into IAM+LTA
• Set of transformations between models
implemented using Xtend language
from openArchitectureWare framework
• Xtext language for IAM+LTA
parser/editor implementation
• Xpand language used to generate
textual input for Uppaal
• Eclipse Modeling Framework – EMF
21. Future Work
• Automatic generation of properties
to be proved by model checking
• Integration with diferent co-design
and co-synthesis tools
• More experiments to explore the
effectivity of the methodology
22. Conclusions
• Transformation between models is
used to generate an internal
representation model
• IAM+LTA is adequate to be used
by formal verification
– behavior and structure
– control/data flow of execution
– timed automata model