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Study of vlsi design methodologies and limitations using cad tools for cmos technology presentation

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Lakshmi Narain College of Technology & Science Bhopal
Lakshmi Narain College of Technology & Science Bhopal
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INFLUENCE 2013 National Conference on Mega Trends in Engineering (August 16 & 17, 2013) “Study of VLSI Design Methodologies and Limitations using CAD tools for CMOS Technology” Presented By: Ayoush Johari VVS Lavanya School of Interdisciplinary Science and Technology School of Interdisciplinary Science and Technology International Institute of Information Technology International Institute of Information Technology Pune, India Pune, India Rakeshwari Pal Department of Electrical and Electronics Engineering Trinity Institute of Technology and Research Bhopal, India
VLSI Technology and Design Drivers Less Power Consumption Less Price/ More Economical More or Less components per board/system Less Price/ More Economical Higher reliability Improved Interconnects More Compactness High Speed of Operation Lesser Manufacturing Costs Area Utilization/compactness Monday, March 03, 2014 VLSI Design Methodologies and Limitations using CAD Tools Source: http://www.gdiamos.net 2
Why not Silicon Compiler ? Reality Ideal Scenario Design Methodology Silicon Compiler Simple Tasks Complex Procedures VLSI designers Lots Of Human Interaction No Human Interaction Spec/Verilog/VHDL Synthesis Testing team Placement Verification Routing CAD developers Circuit on Silicon Process people 3 source : http://www.vlsicad.ucsd.edu/maryjanerwin/psu
View of IC Designer Design parameters by which Design success is measured:  Performance Specifications  Size of Wafer, Die and overall manufacturing cost  Design time including engineering and time to tape out  Ease of Test pattern generation , verification and testability. Proposed Architecture Algorithm Process Technology VLSI CAD Tools Chip for fabrication Figure 1: Generalized View of a IC Designer source: http://ic.engin.brown.edu/classes/EN1600S08/projects.html  Design is a continuous tradeoff between namely 3 parameters namely Price, Power and performance. Monday, March 03, 2014 VLSI Design Methodologies and Limitations using CAD Tools 4
VLSI Design Methodologies Full Custom Design Semi Custom Design Gate Array Design Standard Cell Design FPGA Based Design CPLD Based Design Hardwired Control PLA Based Control HDL Based Design Methodology RT-Level Synthesis IP Cores, SOCs, DSPs, MEMs Monday, March 03, 2014 VLSI Design Methodologies and Limitations using CAD Tools 5
VLSI Design Methodologies  Systematic design methods or the design methodologies are necessary for successfully designing complex digital hardware.  Our design methods usually differ by the number of abstraction levels and the complexities involved.  A Gated array, standard cell design, full custom design, CPLDs FPGAs are some of the design methodologies well known. More Levels of abstraction System Specifications Analysis Synthesis Automation Manual Less Levels of abstraction Final Chip Figure 2: Abstraction hierarchies in VLSI Design Methods Monday, March 03, 2014 VLSI Design Methodologies and Limitations using CAD Tools 6
Design Flow Evolution Past- 250-180nm Monday, March 03, 2014 Present- 90-45nm VLSI Design Methodologies and Limitations using CAD Tools Future 22.5-10nm Source http://www.vlsicad.ucsd.edu/ 7
VLSI Design Complexities VLSI Design is a process of converting an Idea to a Chip. Problem Domain complexity Development Process complexity Choice Domain complexity Testing related complexity Packaging related complexity source: LSI Logic LEA300K ;(0.6 m CMOS) www.lsi.com Monday, March 03, 2014 VLSI Design Methodologies and Limitations using CAD Tools 8
VLSI CAD Tools  Current systems are very complex.  Design abstraction and decomposition is done to manage complexities.  Tools automate the process of converting our design from one abstraction level to another.  Design automation tools improve productivity. Figure 3: Layout of 4004 microprocessor invented by Intel Engineers Federico Faggin, Ted Hoff, and Stanley Mazor source : http://ic.engin.brown.edu/classes/lecture6 The First IC based microprocessor was built using manual design. To get the chip to the market fast CAD tools are indeed needed. Monday, March 03, 2014 VLSI Design Methodologies and Limitations using CAD Tools 9
Classification and Comparison of VLSI CAD Tools 1. High Level Synthesis(HDLs) Open Source/ Licensed S.No. 1 Cadence EDA Licensed Analog and Mixed signal 2 Mentor Graphics EDA Licensed Analog and Mixed signal 3 Synopsys EDA Licensed Analog and Mixed signal 4 Tanner EDA Licensed Analog and Mixed signal 5 Alliance Open Source Mixed Signal Logic to Layout 6 Electric CAD Open Source Mixed Signal Logic to Layout 7 Magic Open Source Mixed Signal Circuit Layout 8 SystemC Open Source Electronic System Level Library for Digital Design 9 2. Logic Synthesis Tools CAD Tool myHDL Open Source Electronic System Level Hardware Description language 3. Circuit Optimization Tools 3.1 Transistor Sizing Tools 3.2 Process Variation Tools 3.3 Stastical Design Tools 4. Layout Tools 4.1 Floorplanning 4.2 Place and Route Type 4.3 Module Generation 4.4 Automatic Cell Placement Routing 5. Layout Extraction Tools Function Complete CAD Flow Complete CAD Flow Complete CAD Flow Complete CAD Flow Table : Comparative study of various open source and licensed set of VLSI EDA tools.[18] 6. Simulation (Spice for circuit level Simulation) 7. Monday, March 03, 2014 Verification Tools Layout Schematic 10
VLSI CAD Tools (Contd..) VLSI CAD Tools Front End Tools Back End Tools Design Capture Tools Synthesis Tools Design Entry Floor Planning Editors Behavioral Synthesis Editors Place & Route VHDL/Verilog RTL Synthesis Simulation Extraction Synthesis LVS, LVL System Verilog / SystemC, Vera FPGA Synthesis ERC,DRC State Charts Physical Synthesis DFT Insertion Pattern Generators FSM Capture Module/Cells Test Generation Format Converters Timing Analysis Logic Synthesis DSP Synthesis Pattern Generators Monday, March 03, 2014 VLSI Design Methodologies and Limitations using CAD Tools 11
VLSI CAD Tools (Contd..) VLSI CAD Tools Analysis Tools Checkers Testing Related Tools Verifiers DRC,ERC Timing Verifier Netlist Compare ATPG ICE/ Hardware Ratio Checker DFT Formal Verifiers Fan-in/ FanOut Checker Power Checker Monday, March 03, 2014 VLSI Design Methodologies and Limitations using CAD Tools 12
Design and Analysis VHDL / Verilog / SystemC compilation/ synthesis mask layout patterns design schematics find wire routes device layout • Design development is facilitated using Computer-Aided Design (CAD) tools source :http://ic.engin.brown.edu/classes/lecture1 Monday, March 03, 2014 VLSI Design Methodologies and Limitations using CAD Tools 13
tape out mask layout patterns mask writer printing test and packaging chip masks dice die wafer • Design development is facilitated using Computer-Aided Design (CAD) tools Monday, March 03, 2014 VLSI Design Methodologies and Limitations using CAD Tools source: http://ic.engin.brown.edu/ 14 classes/lecture1
Simple VLSI CAD Tool Chain Specifications Hardware Description Languages if SEL == “00“ then Y elseif SEL == “01“ then Y elseif SEL == “10“ then Y else Y end if; = = = = A; B; C; D; Schematic Entry 2:1 MUX 2:1 MUX D Synthesis 2:1 MUX C B Y A SEL == 10 SEL == 01 SEL == 00 IC Layout /Area Layout and Routing Cell Library Simulation Verification and timing/ power results Monday, March 03, 2014 VLSI Design Methodologies and Limitations Source: http://ic.engin.brown.edu/classes 15 using CAD Tools
VLSI CAD Tool Vendors [32] [26] [27] [31] [30] [28] [29] Monday, March 03, 2014 VLSI Design Methodologies and Limitations using CAD Tools 16
Typical VLSI Design Flows Source: http://nptel.iitm.ac.in/courses/IIT-MADRAS/CAD_for_VLSI_Design_I/pdf/nptel-cad1-01.pdf Monday, March 03, 2014 VLSI Design Methodologies and Limitations using CAD Tools 17
Source: http://nptel.iitm.ac.in/courses/IIT-MADRAS/CAD_for_VLSI_Design_I/pdf/nptel-cad1-01.pdf Monday, March 03, 2014 VLSI Design Methodologies and Limitations using CAD Tools 18
Design Representation Levels and Associated Formats Design Behavior ISA,C,C++ Architecture SystemC, VHDL, Verilog Micro -Architecture Software and Operating System EDA Servers and Linux, RTOS Digital Hardware (Register Transfer) Gate Level Netlist (Logic Gates & Latches) Layout and Masks (Fabrication Patterns) Monday, March 03, 2014 VLSI Design Methodologies and Limitations using CAD Tools 19
VLSI Design Complexities vs CAD Tools Design Challenges and Priorities Algorithms and CAD Tools Methodology and EDA Flows Process Technology and Monday, March 03, 2014 VLSI Design Methodologies and Limitations Limitations using CAD Tools 20
Limitations and Challenges to Overcome Designer’s Aim – Transfer Design description in one domain into a fully equivalent design descriptions in respective other domains. Fast Prototyping Custom Design Labor Intensive Low Volume High Volume Guiding Design Organization Principles Programmable Interconnects Mask Programmable Gate Arrays Mixed Standard Cell and Custom Cell to CMOS IC Designers. Design investment increasing for a given Monday, March 03, 2014 Programmable Logic Structures Standard Cell Design Design Options available application Programmable Logic Full Custom mask Design Design Time and Cost Decreasing (for given application) VLSI Design Methodologies and Limitations using CAD Tools Performance Increasing, Die Area Decreasing , Power Dissipation increasing 21
Conclusion  VLSI Design – complexities increases as the time progresses .  Design Methodologies and CAD tools are integral parts in VLSI Design and go hand in hand and they evolve based on designer’s needs.  CAD Tools allows the freedom to VLSI Designers to focus on creativity with respect to process technology.  The development in the design tools, collaborative design methods, the role of human factors and integration factors in the design technology marks the outline of various design methodologies. Monday, March 03, 2014 VLSI Design Methodologies and Limitations using CAD Tools 22
References [1] Randal E. Bryant, Kwang-TingCheng , Andrew B Kahang, Kurt Kreutzer, Wojciech Maly,Richard Newton, Lawerance Pileggi, Jan M Rabaey, Alberto SaniovanniVincentelli, “Limitations and Challenges of CAD technology for CMOS VLSI” . [2] Catherine H. Gebotys, Mohamed I. Elmasry,“Vlsi Design Synthesis and Testability”. [3]A.H. Farrahi, D.J. Hathaway, M.Wang and M.Sarrafzadeh, “Quality OF EDA CAD Tools: Definitions, Metrices and Directions”. [4] Anantha Chandrakasan, Isabel Yang, Carlin Veiri, Dimitri Antoniadis, “Design Considerations and tools for Low voltage Digital system Design” [5] Mike Spreitzer “Comparing Structurally different views of a VLSI Design” [6] Catherine H. Gebotys, Mohamed I. Elmasry, “VLSI Design Synthesis and Testibility” [7] T.S. Cheung, K.Asada, K.L. Yip, H. Wong, Y.C. Cheng, “Low Power CMOS Design Methodologies with reduced voltage swing ” [8] K.A. Sumithra Devi, “Algorithms for CAD tools VLSI design” [9] Jan M. Rabaey, Anantha Chandrakasan, Borivoje Nikolic, “Digital Integrated Circuits” , A Design VLSI Design Methodologies and Limitations perspective Second edition Monday, March 03, 2014 23 using CAD Tools
References ( Contd..) 10] Dr. Nicos Bilalis, “Computer Aided Design CAD”, January 2000 edition [11] Course: “Trends in VLSI Design: Methodologies and CAD tools”. Presenter Raj Singh. IC Design group,CEERI,Pilani-333031 [12] P.van der Wolf. “CAD Frameworks: Principle and Architecture” Kluwer Academic Publishers,236pp [13] K.Chaudhary, A.Onawaza, and E.S. Kuh. “Algorithms for Performance Enhancement and Crosstalk Reduction”. In International conference on Computer Aided Design, pages 697702,1993. [14] C.Chen and M.Sarrafzadeh. “Provably Good Algorithm for low power consumption and supply voltages” ”. In International conference on Computer Aided Design, pages 76-79,1999. [15] H.M. Chen, H.Zhou, F.Y.Young, D.F. Wong, H.H. Yang, and N.Sherwani. “Integrated Floorplanning and Interconnect Planning”. ”. In International conference on Computer Aided Design, pages 354-357,November 1999. [16]http://nptel.iitm.ac.in/courses/IIT-MADRAS/CAD_for_VLSI_Design_I/index.php [17] https://www.coursera.org/course/vlsicad/ [18]http://www.vlsiacademy.org/open-source-cad-tools.html 24
References ( Contd..) [19] Static Free Software. July 2004 http://www.staticfreesoft.com [20] Cadence OrCAD Solutions, February2010. http://www.cadence.com/products/orcad [21] Alliance. http://www.asim.lip6.fr/recheche/alliance [22] Magic VLSI Resource. http://www.opencircuitdesign.com/magic [23]Custom IC Design, http://www.cadence.com/products/cic [24] BSIM3- Introduction, www.device.eees.berkeley.edu/~bsim3 [25] IRSIM, http//:opencircuitdesign.com/irsim [26]http://www.cadence.com/_layouts/images/imgbin/header/cadence_logo2.gif [27] http://www.synopsys.com/Style%20Library/homeimages/snps_logo.gif [28] http://www.mosis.com/graphics2/block_logo_2.jpg [29] http://www.tanner.com/images/eda_icon.jpg [30] http://www.magma-da.com/pics/common/logo.gif [31] http://www.shellytech.com/Images/Logos/MentorGraphicsLogo.jpg [32] http://www.rulabinsky.com/steve/plug.gif Monday, March 03, 2014 VLSI Design Methodologies and Limitations using CAD Tools 25
Thank You... Monday, March 03, 2014 VLSI Design Methodologies and Limitations using CAD Tools 26

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Study of vlsi design methodologies and limitations using cad tools for cmos technology presentation

  • 1. INFLUENCE 2013 National Conference on Mega Trends in Engineering (August 16 & 17, 2013) “Study of VLSI Design Methodologies and Limitations using CAD tools for CMOS Technology” Presented By: Ayoush Johari VVS Lavanya School of Interdisciplinary Science and Technology School of Interdisciplinary Science and Technology International Institute of Information Technology International Institute of Information Technology Pune, India Pune, India Rakeshwari Pal Department of Electrical and Electronics Engineering Trinity Institute of Technology and Research Bhopal, India
  • 2. VLSI Technology and Design Drivers Less Power Consumption Less Price/ More Economical More or Less components per board/system Less Price/ More Economical Higher reliability Improved Interconnects More Compactness High Speed of Operation Lesser Manufacturing Costs Area Utilization/compactness Monday, March 03, 2014 VLSI Design Methodologies and Limitations using CAD Tools Source: http://www.gdiamos.net 2
  • 3. Why not Silicon Compiler ? Reality Ideal Scenario Design Methodology Silicon Compiler Simple Tasks Complex Procedures VLSI designers Lots Of Human Interaction No Human Interaction Spec/Verilog/VHDL Synthesis Testing team Placement Verification Routing CAD developers Circuit on Silicon Process people 3 source : http://www.vlsicad.ucsd.edu/maryjanerwin/psu
  • 4. View of IC Designer Design parameters by which Design success is measured:  Performance Specifications  Size of Wafer, Die and overall manufacturing cost  Design time including engineering and time to tape out  Ease of Test pattern generation , verification and testability. Proposed Architecture Algorithm Process Technology VLSI CAD Tools Chip for fabrication Figure 1: Generalized View of a IC Designer source: http://ic.engin.brown.edu/classes/EN1600S08/projects.html  Design is a continuous tradeoff between namely 3 parameters namely Price, Power and performance. Monday, March 03, 2014 VLSI Design Methodologies and Limitations using CAD Tools 4
  • 5. VLSI Design Methodologies Full Custom Design Semi Custom Design Gate Array Design Standard Cell Design FPGA Based Design CPLD Based Design Hardwired Control PLA Based Control HDL Based Design Methodology RT-Level Synthesis IP Cores, SOCs, DSPs, MEMs Monday, March 03, 2014 VLSI Design Methodologies and Limitations using CAD Tools 5
  • 6. VLSI Design Methodologies  Systematic design methods or the design methodologies are necessary for successfully designing complex digital hardware.  Our design methods usually differ by the number of abstraction levels and the complexities involved.  A Gated array, standard cell design, full custom design, CPLDs FPGAs are some of the design methodologies well known. More Levels of abstraction System Specifications Analysis Synthesis Automation Manual Less Levels of abstraction Final Chip Figure 2: Abstraction hierarchies in VLSI Design Methods Monday, March 03, 2014 VLSI Design Methodologies and Limitations using CAD Tools 6
  • 7. Design Flow Evolution Past- 250-180nm Monday, March 03, 2014 Present- 90-45nm VLSI Design Methodologies and Limitations using CAD Tools Future 22.5-10nm Source http://www.vlsicad.ucsd.edu/ 7
  • 8. VLSI Design Complexities VLSI Design is a process of converting an Idea to a Chip. Problem Domain complexity Development Process complexity Choice Domain complexity Testing related complexity Packaging related complexity source: LSI Logic LEA300K ;(0.6 m CMOS) www.lsi.com Monday, March 03, 2014 VLSI Design Methodologies and Limitations using CAD Tools 8
  • 9. VLSI CAD Tools  Current systems are very complex.  Design abstraction and decomposition is done to manage complexities.  Tools automate the process of converting our design from one abstraction level to another.  Design automation tools improve productivity. Figure 3: Layout of 4004 microprocessor invented by Intel Engineers Federico Faggin, Ted Hoff, and Stanley Mazor source : http://ic.engin.brown.edu/classes/lecture6 The First IC based microprocessor was built using manual design. To get the chip to the market fast CAD tools are indeed needed. Monday, March 03, 2014 VLSI Design Methodologies and Limitations using CAD Tools 9
  • 10. Classification and Comparison of VLSI CAD Tools 1. High Level Synthesis(HDLs) Open Source/ Licensed S.No. 1 Cadence EDA Licensed Analog and Mixed signal 2 Mentor Graphics EDA Licensed Analog and Mixed signal 3 Synopsys EDA Licensed Analog and Mixed signal 4 Tanner EDA Licensed Analog and Mixed signal 5 Alliance Open Source Mixed Signal Logic to Layout 6 Electric CAD Open Source Mixed Signal Logic to Layout 7 Magic Open Source Mixed Signal Circuit Layout 8 SystemC Open Source Electronic System Level Library for Digital Design 9 2. Logic Synthesis Tools CAD Tool myHDL Open Source Electronic System Level Hardware Description language 3. Circuit Optimization Tools 3.1 Transistor Sizing Tools 3.2 Process Variation Tools 3.3 Stastical Design Tools 4. Layout Tools 4.1 Floorplanning 4.2 Place and Route Type 4.3 Module Generation 4.4 Automatic Cell Placement Routing 5. Layout Extraction Tools Function Complete CAD Flow Complete CAD Flow Complete CAD Flow Complete CAD Flow Table : Comparative study of various open source and licensed set of VLSI EDA tools.[18] 6. Simulation (Spice for circuit level Simulation) 7. Monday, March 03, 2014 Verification Tools Layout Schematic 10
  • 11. VLSI CAD Tools (Contd..) VLSI CAD Tools Front End Tools Back End Tools Design Capture Tools Synthesis Tools Design Entry Floor Planning Editors Behavioral Synthesis Editors Place & Route VHDL/Verilog RTL Synthesis Simulation Extraction Synthesis LVS, LVL System Verilog / SystemC, Vera FPGA Synthesis ERC,DRC State Charts Physical Synthesis DFT Insertion Pattern Generators FSM Capture Module/Cells Test Generation Format Converters Timing Analysis Logic Synthesis DSP Synthesis Pattern Generators Monday, March 03, 2014 VLSI Design Methodologies and Limitations using CAD Tools 11
  • 12. VLSI CAD Tools (Contd..) VLSI CAD Tools Analysis Tools Checkers Testing Related Tools Verifiers DRC,ERC Timing Verifier Netlist Compare ATPG ICE/ Hardware Ratio Checker DFT Formal Verifiers Fan-in/ FanOut Checker Power Checker Monday, March 03, 2014 VLSI Design Methodologies and Limitations using CAD Tools 12
  • 13. Design and Analysis VHDL / Verilog / SystemC compilation/ synthesis mask layout patterns design schematics find wire routes device layout • Design development is facilitated using Computer-Aided Design (CAD) tools source :http://ic.engin.brown.edu/classes/lecture1 Monday, March 03, 2014 VLSI Design Methodologies and Limitations using CAD Tools 13
  • 14. tape out mask layout patterns mask writer printing test and packaging chip masks dice die wafer • Design development is facilitated using Computer-Aided Design (CAD) tools Monday, March 03, 2014 VLSI Design Methodologies and Limitations using CAD Tools source: http://ic.engin.brown.edu/ 14 classes/lecture1
  • 15. Simple VLSI CAD Tool Chain Specifications Hardware Description Languages if SEL == “00“ then Y elseif SEL == “01“ then Y elseif SEL == “10“ then Y else Y end if; = = = = A; B; C; D; Schematic Entry 2:1 MUX 2:1 MUX D Synthesis 2:1 MUX C B Y A SEL == 10 SEL == 01 SEL == 00 IC Layout /Area Layout and Routing Cell Library Simulation Verification and timing/ power results Monday, March 03, 2014 VLSI Design Methodologies and Limitations Source: http://ic.engin.brown.edu/classes 15 using CAD Tools
  • 16. VLSI CAD Tool Vendors [32] [26] [27] [31] [30] [28] [29] Monday, March 03, 2014 VLSI Design Methodologies and Limitations using CAD Tools 16
  • 17. Typical VLSI Design Flows Source: http://nptel.iitm.ac.in/courses/IIT-MADRAS/CAD_for_VLSI_Design_I/pdf/nptel-cad1-01.pdf Monday, March 03, 2014 VLSI Design Methodologies and Limitations using CAD Tools 17
  • 18. Source: http://nptel.iitm.ac.in/courses/IIT-MADRAS/CAD_for_VLSI_Design_I/pdf/nptel-cad1-01.pdf Monday, March 03, 2014 VLSI Design Methodologies and Limitations using CAD Tools 18
  • 19. Design Representation Levels and Associated Formats Design Behavior ISA,C,C++ Architecture SystemC, VHDL, Verilog Micro -Architecture Software and Operating System EDA Servers and Linux, RTOS Digital Hardware (Register Transfer) Gate Level Netlist (Logic Gates & Latches) Layout and Masks (Fabrication Patterns) Monday, March 03, 2014 VLSI Design Methodologies and Limitations using CAD Tools 19
  • 20. VLSI Design Complexities vs CAD Tools Design Challenges and Priorities Algorithms and CAD Tools Methodology and EDA Flows Process Technology and Monday, March 03, 2014 VLSI Design Methodologies and Limitations Limitations using CAD Tools 20
  • 21. Limitations and Challenges to Overcome Designer’s Aim – Transfer Design description in one domain into a fully equivalent design descriptions in respective other domains. Fast Prototyping Custom Design Labor Intensive Low Volume High Volume Guiding Design Organization Principles Programmable Interconnects Mask Programmable Gate Arrays Mixed Standard Cell and Custom Cell to CMOS IC Designers. Design investment increasing for a given Monday, March 03, 2014 Programmable Logic Structures Standard Cell Design Design Options available application Programmable Logic Full Custom mask Design Design Time and Cost Decreasing (for given application) VLSI Design Methodologies and Limitations using CAD Tools Performance Increasing, Die Area Decreasing , Power Dissipation increasing 21
  • 22. Conclusion  VLSI Design – complexities increases as the time progresses .  Design Methodologies and CAD tools are integral parts in VLSI Design and go hand in hand and they evolve based on designer’s needs.  CAD Tools allows the freedom to VLSI Designers to focus on creativity with respect to process technology.  The development in the design tools, collaborative design methods, the role of human factors and integration factors in the design technology marks the outline of various design methodologies. Monday, March 03, 2014 VLSI Design Methodologies and Limitations using CAD Tools 22
  • 23. References [1] Randal E. Bryant, Kwang-TingCheng , Andrew B Kahang, Kurt Kreutzer, Wojciech Maly,Richard Newton, Lawerance Pileggi, Jan M Rabaey, Alberto SaniovanniVincentelli, “Limitations and Challenges of CAD technology for CMOS VLSI” . [2] Catherine H. Gebotys, Mohamed I. Elmasry,“Vlsi Design Synthesis and Testability”. [3]A.H. Farrahi, D.J. Hathaway, M.Wang and M.Sarrafzadeh, “Quality OF EDA CAD Tools: Definitions, Metrices and Directions”. [4] Anantha Chandrakasan, Isabel Yang, Carlin Veiri, Dimitri Antoniadis, “Design Considerations and tools for Low voltage Digital system Design” [5] Mike Spreitzer “Comparing Structurally different views of a VLSI Design” [6] Catherine H. Gebotys, Mohamed I. Elmasry, “VLSI Design Synthesis and Testibility” [7] T.S. Cheung, K.Asada, K.L. Yip, H. Wong, Y.C. Cheng, “Low Power CMOS Design Methodologies with reduced voltage swing ” [8] K.A. Sumithra Devi, “Algorithms for CAD tools VLSI design” [9] Jan M. Rabaey, Anantha Chandrakasan, Borivoje Nikolic, “Digital Integrated Circuits” , A Design VLSI Design Methodologies and Limitations perspective Second edition Monday, March 03, 2014 23 using CAD Tools
  • 24. References ( Contd..) 10] Dr. Nicos Bilalis, “Computer Aided Design CAD”, January 2000 edition [11] Course: “Trends in VLSI Design: Methodologies and CAD tools”. Presenter Raj Singh. IC Design group,CEERI,Pilani-333031 [12] P.van der Wolf. “CAD Frameworks: Principle and Architecture” Kluwer Academic Publishers,236pp [13] K.Chaudhary, A.Onawaza, and E.S. Kuh. “Algorithms for Performance Enhancement and Crosstalk Reduction”. In International conference on Computer Aided Design, pages 697702,1993. [14] C.Chen and M.Sarrafzadeh. “Provably Good Algorithm for low power consumption and supply voltages” ”. In International conference on Computer Aided Design, pages 76-79,1999. [15] H.M. Chen, H.Zhou, F.Y.Young, D.F. Wong, H.H. Yang, and N.Sherwani. “Integrated Floorplanning and Interconnect Planning”. ”. In International conference on Computer Aided Design, pages 354-357,November 1999. [16]http://nptel.iitm.ac.in/courses/IIT-MADRAS/CAD_for_VLSI_Design_I/index.php [17] https://www.coursera.org/course/vlsicad/ [18]http://www.vlsiacademy.org/open-source-cad-tools.html 24
  • 25. References ( Contd..) [19] Static Free Software. July 2004 http://www.staticfreesoft.com [20] Cadence OrCAD Solutions, February2010. http://www.cadence.com/products/orcad [21] Alliance. http://www.asim.lip6.fr/recheche/alliance [22] Magic VLSI Resource. http://www.opencircuitdesign.com/magic [23]Custom IC Design, http://www.cadence.com/products/cic [24] BSIM3- Introduction, www.device.eees.berkeley.edu/~bsim3 [25] IRSIM, http//:opencircuitdesign.com/irsim [26]http://www.cadence.com/_layouts/images/imgbin/header/cadence_logo2.gif [27] http://www.synopsys.com/Style%20Library/homeimages/snps_logo.gif [28] http://www.mosis.com/graphics2/block_logo_2.jpg [29] http://www.tanner.com/images/eda_icon.jpg [30] http://www.magma-da.com/pics/common/logo.gif [31] http://www.shellytech.com/Images/Logos/MentorGraphicsLogo.jpg [32] http://www.rulabinsky.com/steve/plug.gif Monday, March 03, 2014 VLSI Design Methodologies and Limitations using CAD Tools 25
  • 26. Thank You... Monday, March 03, 2014 VLSI Design Methodologies and Limitations using CAD Tools 26