1. http://www.bized.co.uk
Session 2
Prepared by
Alaa Salah Shehata
Mahmoud A. M. Abd El Latif
Mohamed Mohamed Tala’t
Mohamed Salah Mahmoud
Version 02 – October 2011
Copyright 2006 – Biz/ed
3. Session 2
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Refresh Your Memory Answer
library IEEE;
USE ieee.std_logic_1164.all;
Entity AND_GATE is
Port (
X1 : in std_logic_vector(4 downto 0 );
X2 : in std_logic_vector(4 downto 0 );
Y : out std_logic_vector(4 downto 0 )
);
END AND_GATE;
Architecture Behave of AND_GATE IS
begin
Y <= X1 AND X2 ;
END Behave ;
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7. Session 2
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Combinational Vs. Sequential logic circuit
in any digital system we can divide the circuits into two
types :
Combinational logic circuits
implement Boolean functions, so the output in this
circuits is function only on their inputs, and are not
based on clocks.
Sequential circuits
compute their output based on input and state, and that
the state is updated based on a clock.
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Signals
Signals used to connect between systems or connect components inside systems
Types of signals
--External Signals
-In,Out ports
-Internal connections in structuraldiscussed later
--Internal Signals
-connect devices inside the block
-used for Intermediate calculations
Note
We use Internal Signals for:
Avoid illegal port usage situations like Read Output port
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Signals
Signal declaration
architecture <arch_name> of <entity_name> is
-- architecture declarations
signal <sig_name> : <sig_type>;
.
.
.
begin
<Architecture body>
End <arch_name> ;
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• NAND Gate
A
C D
B Example
5
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NAND Gate
LIBRARY ieee;
USE ieee.std_logic_1164.all;
A
ENTITY NAND_GATE IS C D
port ( A : in STD_LOGIC;
B : in STD_LOGIC;
B
D : out STD_LOGIC
);
END ENTITY NAND_GATE ;
ARCHITECTURE behave OF NAND_GATE IS
SIGNAL C : std_logic;
BEGIN
C <= A and B ;
D <= not C ;
END behave;
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• Write the VHDL code for this logic circuit
A
D
B Exercise
1
C
D F
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13. Session 2
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Write the VHDL code for this logic circuit
A
LIBRARY ieee;
USE ieee.std_logic_1164.all; SIG_1 G
B
ENTITY NAND_GATE IS
port ( A,B,C,D : in STD_LOGIC;
G,F : out STD_LOGIC
);
END ENTITY NAND_GATE ; C SIG_2
ARCHITECTURE behave OF NAND_GATE IS
SIGNAL SIG_1 : std_logic; F
SIGNAL SIG_2 : std_logic; D
BEGIN
SIG_1 <= A and B ;
SIG_2 <= SIG_1 and C ;
F <= SIG_2 and D ;
G <= SIG_1 ;
END behave;
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•VHDL has concurrent statements
and sequential statements
•Concurrent statements are executed
in parallel w.r.t each other.
With – select
When – else
Process statement
Assign statement
•Sequential statements are executed
in sequence w.r.t each other.
Statements
•Sequential statements should be
written inside a “process”
If statement
loop statement
Case statement
Wait and Null statement
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Process
-What is a Process
Process allows writing sequential statements within concurrent environment
Process is like a container that include the sequential statements
Process declaration
process (sensitivity list)
begin
sequential statements ;
end process ;
Note
<sensitivity_list>:
List of signals/ports that cause the process to be executed whenever there is a
change in their values
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Process
Architecture behave of comb_ct is
Begin
process (x,y)
begin
z <= x and y;
h <= x or y;
t <= x xor y;
…
end process;
End behave ;
Statements inside a “process” are read sequentially and executed
when the process suspends (“end process” is reached)
very important note:
What is this statement differs from z<= x and y;
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Question
Statements shown at left are inside a process and at right are outside it what
is the result in the two cases
Process ()
begin
A <= B ; A <= B ;
A <= C ; A <= C ;
end
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Question
Statements shown at left are inside a process and at right are outside it what
is the result in the two cases
Architecture Architecture
Process () begin
begin A <= B ;
A <= B ; A <= C ;
A <= C ; end
end
end
B B
A
A
C A C
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Question
Statements shown at left are inside a process and at right are outside it what
is the result in the two cases
Process ()
begin
A <= B ; A <= B ;
B <= A ; B <= A ;
end
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IF Statement
Executes a list of sequential statements when the corresponding condition
evaluates to true
V.IMPORTANT ROLE
The branches order is important as they imply a priority
Syntax
If <condition> then
-- list of sequential statements
elsif <condition> then
-- list of sequential statements
else
-- list of sequential statements
end if;
<condition> Boolean expression that evaluates to either TRUE or FALSE
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• Adder/Subtractor
A
Result
B Adder_Subtractor
Example
6
Operation
Operation =1 a+b
Operation =0 a-b
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Adder/Subtractor
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
ENTITY add_sub IS
port ( a, b : in integer;
result : out integer;
operation : in std_logic); -- add or subtract
END ENTITY add_sub;
ARCHITECTURE behave OF add_sub IS
BEGIN
process ( a, b, operation
What is sensitivity list !! )
begin
if (operation = '1') then -- Add when operation = '1'
result <= a + b;
else -- Subtract otherwise
result <= a - b;
end if;
end process;
END ARCHITECTURE behave;
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Adder/Subtractor
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
ENTITY add_sub IS
port ( a, b : in integer;
result : out integer;
operation : in std_logic); -- add or subtract
END ENTITY add_sub;
ARCHITECTURE behave OF add_sub IS
BEGIN
process ( a, b, operation )
begin
if (operation = '1') then -- Add when operation = '1'
result <= a + b;
else -- Subtract otherwise
result <= a - b;
end if;
end process;
END ARCHITECTURE behave;
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• Simple Comparator
A
C
B Comparator
Example
7
A=B C=“00”
A>B C=“01”
A<B C=“10”
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Simple Comparator
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY comparator IS
port( a, b : in std_logic_vector(7 downto 0);
c : out std_logic_vector(1 downto 0);
);
END ENTITY;
ARCHITECTURE behave OF comparator IS
BEGIN
process (a, b)
begin
if (A = B ) then -- equality
c <= "00";
elsif (A > B) then -- greater than
c <= "01";
elsif (A < B) then -- greater than
c <= "10";
else -- covers other cases
c <= “ZZ";
end if;
end process;
END ARCHITECTURE;
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CASE Statement
Makes several conditions on the same signal
Syntax
case <expression> is
when <choice> =>
-- list of sequential statements
when <choice> =>
-- list of sequential statements
when others =>
-- list of sequential statements
end case;
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CASE Statement
<expression> can be a signal or a variable (discussed later)
<choice> constants representing one of possible <expression> values.
V.IMPORTANT ROLE
-“When others” is a must if not all values of <expression> are covered
-Each branch of a Case statement can have any number of sequential statements
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• 4 x 1 Multiplexer
Example
8
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4 x 1 Multiplexer
Architecture rtl of mux_case is
begin
process (a,b,c,d,sel)
begin
Case sel is
When "00" =>
f <= a;
When "01" =>
f <= b; Do we need all these signals? On sensitivity list ??
When "10" =>
f <= c;
When "11" =>
f <= d;
when others => -- is "when others" a must?
f <= „Z‟;
End case;
End process;
End architecture;
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• Simulate 2 x 4 Decoder on Modelsim
lab
1
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31. Session 2
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2 x 4 Decoder
Architecture rtl of dec is
begin
process (a)
begin
Case a is
When "00" =>
f <= “0001”;
When "01" =>
f <= “0010”;
When "10" =>
f <= “0100”;
When "11" =>
f <= “1000”;
when others =>
f <= “ZZZZ”;
End case;
End process;
End rtl ; How to make 4 x 2 Encoder !
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1-Area Optimization
During writing a code for implementation you must save your resources
Example
Write a code describing this Adder
OpSel Function
00 A+B
01 C+D
10 E+F
11 G+H
Note that the selector can select one addition at a time, the operators are mutually
exclusive
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It is better to write a code that describe the circuit on the right as adders take much bigger
area than multiplexers
his transformation of operators is called Resource Sharing
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Possible solutions
Solution 1
process (OpSel,A,B,C,D,E,F,G,H)
begin
case OpSel is
when "00" => Z <= A + B ;
when "01" => Z <= C + D ;
when "10" => Z <= E + F ;
when "11" => Z <= G + H ;
when others => Z <= (others => 'X') ;
end case ;
end process ;
Here the code is Tool Driven Resource Sharing, the tool understand that we don’t need to
make four adders and one Adder is implemented.
General Note
To ensure resource sharing, operators must be coded in the same process, and same code
(case or if) structure.
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Solution 2
X <= Mux4(OpSel, A, C, E, G) ;
Y <= Mux4(OpSel, B, D, F, H) ;
Z <= X + Y ;
Here the code is Code Driven Resource Sharing, You forced the tool to use only one Adder.
Solution 3
Process (OpSel, A, B, C, D, E, F, G, H)
begin
if (OpSel = "00") then Z <= A + B; end if;
if (OpSel = "01") then Z <= C + D; end if;
if (OpSel = "10") then Z <= E + F; end if;
if (OpSel = "11") then Z <= G + H; end if;
end process ;
Bad Code that may defeat Resource Sharing.
Synthesis tool may create a separate resource for each adder. Don’t do that!
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36. Session 2
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Sequential Circuits
Clock period
A digital clock signal is a square wave voltage.
In complex circuits a clock with a fixed frequency is used for timing.
To store and pass the data or digital signals through, some specific gates are used which
are called latches or flip-flops. These are some kind of memory that store their input over
their output by a specific level or edge of the clock.
Asynchronous Operation
don’t wait clock
Synchronous
wait clock to get an input and to produce an output
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38. Session 2
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• Simple D-Flip Flop
D
Q
D_FF
Example
9
clk
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Simple D-FF
Library ieee;
use ieee.std_logic_1164.all;
Entity d_ff is
Port( D, clk : in std_logic;
Q : out std_logic );
end entity;
Architecture behav of d_ff is
Begin
process(clk)
begin
rising_edge() : defined for std_logic type
if rising_edge(clk) then
Q <= D;
end if;
end process;
end behav;
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• D-FF
with Asynchronous reset
D
Q
Reset D_FF
Example
10
clk
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D-FF with Asynchronous reset
Library ieee;
use ieee.std_logic_1164.all;
Entity d_ff is
Port( d, clk, rst : in std_logic;
Q : out std_logic);
end entity;
Architecture behav of d_ff is
Begin
process(clk, rst)
begin
If (rst = '1') then Since rst has higher priority over the clk edge
Q <= '0'; We put it on sensitivity list
elsif rising_edge(clk) then
Q <= d; We have now a D Flip Flop with asynchronous
end if; reset
end process;
end behav;
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• D-FF
with Asynchronous reset
and Synchronous enable
D
Q
Reset D_FF
Example
enable 11
clk
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D-FF with Asynchronous reset and Synchronous enable
Library ieee;
use ieee.std_logic_1164.all;
Reset Clk Enable Q+
Entity d_ff is
1 - - 0
Port( d, clk, rst,en : in std_logic;
Q : out std_logic 0 No rising_edge - Q
); 0 Rising_edge 0 Q
end entity; 0 Rising_edge 1 D
Architecture behav of d_ff is
Begin
process(clk, rst)
begin
If (rst = '1') then Enable has lower priority w.r.t the clk edge
Q <= '0'; So we don’t put it in sensitivity list as it will slow the
elsif rising_edge(clk) then simulation
If (en = '1') then
Q <= d;
end if; We have now a D Flip Flop with asynchronous
end if; reset and synchronous enable
end process;
end behav;
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D-Latch vs D-Flip Flop
With a latch, a signal can’t propagate through until the clock is high .
With a Flip-flop, the signal only propagates through on the rising edge.
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D-Latch with Asynchronous reset and Synchronous enable
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity d_ff is
port( clk,reset,enable: in std_logic;
d: in std_logic;
q: out std_logic);
end d_ff;
architecture Behavioral of d_ff is
begin
process(clk,reset,d)
begin
if reset = '1' then
q<= '0';
elsif clk = '1' then
if enable = '1' then
q<= d;
end if;
end if;
end process;
end Behavioral;
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Assignment
Session-2
Write a code describing a T-Flip Flop
T
If the T input is high, the T flip-flop changes Q
state ("toggles") whenever the clock input is
stored. If the T input is low, the flip-flop holds Reset D_FF
the previous value. Q’
clk
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49. Session 2
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ALU Arithmetic Logic Unit
It is a circuit capable of executing both kinds of operations, arithmetic as well as
logical.
Its operation is described next slide as follow :
The output (arithmetic or logical) is selected by the MSB of sel
The specific operation is selected by sel’s other three bits.
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Sel Operation Function Unit
0000 Y<= a Transfer A
0001 Y<= a+1 Increment A
0010 Y<= a-1 Decrement A
0011 Y<= b Transfer B
Athematic
0100 Y<= b+1 Increment A
0101 Y<= b-1 Decrement A
0110 Y<= a+b Add a and b
0111 Y<= a+b+cin Add a and b and carry
1000 Y<= not a Complement a
1001 Y<= not b Complement b
1010 Y<= a AND b AND
1011 Y<= a OR b OR
logic
1100 Y<= a NAND b NAND
1101 Y<= a NOR b NOR
1110 Y<= a XOR b XOR
1111 Y<= a XNOR b XNOR
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Required
-VHDL code of this ALU
-Verify functionality using Modelsim
Deadline
-Next session
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52. Session 2
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Download Session 2 material
Session 2.pdf
Modelsim tuotorial.pdf
Xilinx ISE tuotorial.pdf
lab1.txt
Ask for the material through mail
start.courses@gmail.com
Facebook group
start.group@groups.facebook.com
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