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Von Neumann Architecture Main Memory Output Devices Input Devices Backing Storage
The Processor Arithmetic and Logic Unit (ALU) Carries out calculations e.g. 10110011 + 11110010 Performs logical operations e.g. AND, OR, NOT ALU
The Processor Control Unit Manages the  fetching decoding and executing of instructions ALU Control Unit
The Processor Registers ,[object Object],[object Object],[object Object],[object Object],ALU Control Unit Memory Data Register Memory Address Register Other Registers
The Processor Internal Buses Used to transmit information ALU Control Unit Memory Data Register Memory Address Register Other Registers
The Processor & Main Memory Processor Main Memory Address 00000000 00000001 00000010 00000011 00000100 00000101 00000110 00000111 00001000 00001001 Address Bus 32 Lines Data Bus 16 Lines Control Bus 6 Lines Each memory location is represented by a unique address. ALU Control Unit Memory Data Register Memory Address Register Other Registers
The Address Bus Memory Address Register Processor Main Memory Address 00000000 00000001 00000010 00000011 00000100 00000101 00000110 00000111 00001000 00001001 Address Bus ,[object Object],[object Object],[object Object]
The Address Bus Memory Address Register Processor Main Memory Address 00000000 00000001 00000010 00000011 00000100 00000101 00000110 00000111 00001000 00001001 Address Bus ,[object Object],[object Object],[object Object]
The Data Bus Memory Data Register Processor Main Memory 11110011 Address 00000000 00000001 00000010 00000011 00000100 00000101 00000110 00000111 00001000 00001001 Data Bus ,[object Object],[object Object],[object Object]
The Data Bus Memory Data Register Processor Main Memory 11110011 Address 00000000 00000001 00000010 00000011 00000100 00000101 00000110 00000111 00001000 00001001 Data Bus ,[object Object],[object Object]
The Control Bus Control Unit Processor Main Memory Address 00000000 00000001 00000010 00000011 00000100 00000101 00000110 00000111 00001000 00001001 Control Bus Each wire on the bus has its own separate function and is activated independently of the others Read Informs the memory that data is to be sent to the processor from a particular memory location Write Informs the memory that data is to be stored in a particular memory location Clock Generates a constant pulse which regulates the flow of information A clock of 600MHz (megahertz) generates a pulse 600,000,000 times a second
The Control Bus Control Unit Processor Main Memory Address 00000000 00000001 00000010 00000011 00000100 00000101 00000110 00000111 00001000 00001001 Control Bus Each wire on the bus has its own separate function and is activated independently of the others Interrupt A message from a peripheral device causes the processor to stop processing the current task.  Current data is stored in a temporary area called the stack.  The processor deals with the interrupt.  The data is then retrieved from the stack and the task is resumed Reset Clears all internal processor registers and returns the computer to its initial switched on state
The Fetch-Execute Cycle To execute a program you must first load the program and any relevant data in to the computer’s memory (RAM) from disk.  The program and data is stored in memory until needed by the processor (the stored program concept). A program may contain thousands of instructions but the processor can only execute one instruction at a time.  The first instruction is fetched from memory in to the processor where it is decoded and executed.  Then the second instruction is fetched and then executed and so on until the program ends.  This is known as the  FETCH – EXECUTE CYCLE .
Memory Read Operation Processor Main Memory Address 00000000 00000001 00000010 00000011 00000100 00000101 00000110 00000111 00001000 00001001 Address Bus Data Bus Control Bus 1.  The processor sets up the  address bus  with the required memory address by placing it in the  MAR ALU Control Unit Memory Data Register Memory Address Register Other Registers
Memory Read Operation Processor Main Memory Address 00000000 00000001 00000010 00000011 00000100 00000101 00000110 00000111 00001000 00001001 Address Bus Data Bus Control Bus 2.  The  control unit  activates the  read line  on the control bus ALU Control Unit Memory Data Register Memory Address Register Other Registers
Memory Read Operation Processor Main Memory Address 00000000 00000001 00000010 00000011 00000100 00000101 00000110 00000111 00001000 00001001 Address Bus Data Bus Control Bus 3.  The  address bus   opens the relevant memory location at that address 11110011 ALU Control Unit Memory Data Register Memory Address Register Other Registers
Memory Read Operation Processor Main Memory Address 00000000 00000001 00000010 00000011 00000100 00000101 00000110 00000111 00001000 00001001 Address Bus Data Bus Control Bus 4.  The contents of the memory location are released, sent along the  data bus  and into the  MDR 11110011 ALU Control Unit Memory Data Register Memory Address Register Other Registers
Memory Read Operation Processor Main Memory Address 00000000 00000001 00000010 00000011 00000100 00000101 00000110 00000111 00001000 00001001 Address Bus Data Bus Control Bus 5.  The data is then  decoded  and  executed ALU Control Unit Memory Data Register Memory Address Register Other Registers
Memory Write Operation Processor Main Memory Address 00000000 00000001 00000010 00000011 00000100 00000101 00000110 00000111 00001000 00001001 Address Bus Data Bus Control Bus 1.  The processor sets up the  address bus  with the required memory address by placing it in the  MAR ALU Control Unit Memory Data Register Memory Address Register Other Registers
Memory Write Operation Processor Main Memory Address 00000000 00000001 00000010 00000011 00000100 00000101 00000110 00000111 00001000 00001001 Address Bus Data Bus Control Bus 2.  The processor sets up the  data bus  with the value to be stored in memory by placing it in the  MDR ALU Control Unit Memory Data Register Memory Address Register Other Registers
Memory Write Operation Processor Main Memory Address 00000000 00000001 00000010 00000011 00000100 00000101 00000110 00000111 00001000 00001001 Address Bus Data Bus Control Bus 3.  The  control unit  activates the  write line  on the control bus ALU Control Unit Memory Data Register Memory Address Register Other Registers
Memory Write Operation Processor Main Memory Address 00000000 00000001 00000010 00000011 00000100 00000101 00000110 00000111 00001000 00001001 Address Bus Data Bus Control Bus 4.  The address bus opens the relevant memory location at that address ALU Control Unit Memory Data Register Memory Address Register Other Registers
Memory Write Operation Processor Main Memory Address 00000000 00000001 00000010 00000011 00000100 00000101 00000110 00000111 00001000 00001001 Address Bus Data Bus Control Bus 5.  The contents of the memory location are released, sent along the  data bus  and into the  memory location 11000111 ALU Control Unit Memory Data Register Memory Address Register Other Registers
Credits ,[object Object],[object Object],[object Object],[object Object],[object Object]

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The Processor

  • 1.  
  • 2. Von Neumann Architecture Main Memory Output Devices Input Devices Backing Storage
  • 3. The Processor Arithmetic and Logic Unit (ALU) Carries out calculations e.g. 10110011 + 11110010 Performs logical operations e.g. AND, OR, NOT ALU
  • 4. The Processor Control Unit Manages the fetching decoding and executing of instructions ALU Control Unit
  • 5.
  • 6. The Processor Internal Buses Used to transmit information ALU Control Unit Memory Data Register Memory Address Register Other Registers
  • 7. The Processor & Main Memory Processor Main Memory Address 00000000 00000001 00000010 00000011 00000100 00000101 00000110 00000111 00001000 00001001 Address Bus 32 Lines Data Bus 16 Lines Control Bus 6 Lines Each memory location is represented by a unique address. ALU Control Unit Memory Data Register Memory Address Register Other Registers
  • 8.
  • 9.
  • 10.
  • 11.
  • 12. The Control Bus Control Unit Processor Main Memory Address 00000000 00000001 00000010 00000011 00000100 00000101 00000110 00000111 00001000 00001001 Control Bus Each wire on the bus has its own separate function and is activated independently of the others Read Informs the memory that data is to be sent to the processor from a particular memory location Write Informs the memory that data is to be stored in a particular memory location Clock Generates a constant pulse which regulates the flow of information A clock of 600MHz (megahertz) generates a pulse 600,000,000 times a second
  • 13. The Control Bus Control Unit Processor Main Memory Address 00000000 00000001 00000010 00000011 00000100 00000101 00000110 00000111 00001000 00001001 Control Bus Each wire on the bus has its own separate function and is activated independently of the others Interrupt A message from a peripheral device causes the processor to stop processing the current task. Current data is stored in a temporary area called the stack. The processor deals with the interrupt. The data is then retrieved from the stack and the task is resumed Reset Clears all internal processor registers and returns the computer to its initial switched on state
  • 14. The Fetch-Execute Cycle To execute a program you must first load the program and any relevant data in to the computer’s memory (RAM) from disk. The program and data is stored in memory until needed by the processor (the stored program concept). A program may contain thousands of instructions but the processor can only execute one instruction at a time. The first instruction is fetched from memory in to the processor where it is decoded and executed. Then the second instruction is fetched and then executed and so on until the program ends. This is known as the FETCH – EXECUTE CYCLE .
  • 15. Memory Read Operation Processor Main Memory Address 00000000 00000001 00000010 00000011 00000100 00000101 00000110 00000111 00001000 00001001 Address Bus Data Bus Control Bus 1. The processor sets up the address bus with the required memory address by placing it in the MAR ALU Control Unit Memory Data Register Memory Address Register Other Registers
  • 16. Memory Read Operation Processor Main Memory Address 00000000 00000001 00000010 00000011 00000100 00000101 00000110 00000111 00001000 00001001 Address Bus Data Bus Control Bus 2. The control unit activates the read line on the control bus ALU Control Unit Memory Data Register Memory Address Register Other Registers
  • 17. Memory Read Operation Processor Main Memory Address 00000000 00000001 00000010 00000011 00000100 00000101 00000110 00000111 00001000 00001001 Address Bus Data Bus Control Bus 3. The address bus opens the relevant memory location at that address 11110011 ALU Control Unit Memory Data Register Memory Address Register Other Registers
  • 18. Memory Read Operation Processor Main Memory Address 00000000 00000001 00000010 00000011 00000100 00000101 00000110 00000111 00001000 00001001 Address Bus Data Bus Control Bus 4. The contents of the memory location are released, sent along the data bus and into the MDR 11110011 ALU Control Unit Memory Data Register Memory Address Register Other Registers
  • 19. Memory Read Operation Processor Main Memory Address 00000000 00000001 00000010 00000011 00000100 00000101 00000110 00000111 00001000 00001001 Address Bus Data Bus Control Bus 5. The data is then decoded and executed ALU Control Unit Memory Data Register Memory Address Register Other Registers
  • 20. Memory Write Operation Processor Main Memory Address 00000000 00000001 00000010 00000011 00000100 00000101 00000110 00000111 00001000 00001001 Address Bus Data Bus Control Bus 1. The processor sets up the address bus with the required memory address by placing it in the MAR ALU Control Unit Memory Data Register Memory Address Register Other Registers
  • 21. Memory Write Operation Processor Main Memory Address 00000000 00000001 00000010 00000011 00000100 00000101 00000110 00000111 00001000 00001001 Address Bus Data Bus Control Bus 2. The processor sets up the data bus with the value to be stored in memory by placing it in the MDR ALU Control Unit Memory Data Register Memory Address Register Other Registers
  • 22. Memory Write Operation Processor Main Memory Address 00000000 00000001 00000010 00000011 00000100 00000101 00000110 00000111 00001000 00001001 Address Bus Data Bus Control Bus 3. The control unit activates the write line on the control bus ALU Control Unit Memory Data Register Memory Address Register Other Registers
  • 23. Memory Write Operation Processor Main Memory Address 00000000 00000001 00000010 00000011 00000100 00000101 00000110 00000111 00001000 00001001 Address Bus Data Bus Control Bus 4. The address bus opens the relevant memory location at that address ALU Control Unit Memory Data Register Memory Address Register Other Registers
  • 24. Memory Write Operation Processor Main Memory Address 00000000 00000001 00000010 00000011 00000100 00000101 00000110 00000111 00001000 00001001 Address Bus Data Bus Control Bus 5. The contents of the memory location are released, sent along the data bus and into the memory location 11000111 ALU Control Unit Memory Data Register Memory Address Register Other Registers
  • 25.