Personal Information
Entreprise/Lieu de travail
Bengaluru Area, India India
Profession
Senior Staff Engr. at PMC Sierra India, & Senior Member-IEEE
Secteur d’activité
Electronics / Computer Hardware
Site Web
http://www.pmc-sierra.com/
À propos
* Top Level Partitioning and Integration (Top to Bottom/Bottom to Top Flow).
* Floorplanning, CTS, Placement & Routing.
* Power & IR Drop Analysis.
* Physical Verification.
* DFM Closure.
* Static Timing, Xtalk Analysis.
* Algorithm developments on Physical Design.
* Mixed Signal Top Level Physical Integration.
* Experienced on Application Specific Instruction-set Processors (ASIP).
----------------
Specialties:
----------------
* Physical Design Implementation.
* SoC Integration.
* Hands-on Experience on multiple nodes - 28nm, 40/45nm, 65nm, 90nm, 130nm.
---------------------------------------
Presentations (Public Domain)
---------------------------------------
Mots-clés
devanshu
vlsi
management
pmc sierra
physical design
semiconductor
nxp
soc
bangalore
bangalore metro
rfid
mifare
smart cards
storage
sas
san
networking
talus
icc
magma
cadence
soc encounter
synopsys
atoptech
bits pilani
architecture
philips
hdtv ic
asic
license servers
ic design project management
semiconductors
perl
p&r
ic physical design
de bono
google
six hats
technical
resource
technical management
project management
one minute management
time management
Tout plus
Présentations
(8)J’aime
(3)44CON 2014 - Stupid PCIe Tricks, Joe Fitzpatrick
44CON
•
il y a 9 ans
HDTV Chip From NXP (PNX85500)
Devanshu Shrivastava
•
il y a 10 ans
PM8056 Chip SAS Expander from PMC Sierra
Devanshu Shrivastava
•
il y a 10 ans
Personal Information
Entreprise/Lieu de travail
Bengaluru Area, India India
Profession
Senior Staff Engr. at PMC Sierra India, & Senior Member-IEEE
Secteur d’activité
Electronics / Computer Hardware
Site Web
http://www.pmc-sierra.com/
À propos
* Top Level Partitioning and Integration (Top to Bottom/Bottom to Top Flow).
* Floorplanning, CTS, Placement & Routing.
* Power & IR Drop Analysis.
* Physical Verification.
* DFM Closure.
* Static Timing, Xtalk Analysis.
* Algorithm developments on Physical Design.
* Mixed Signal Top Level Physical Integration.
* Experienced on Application Specific Instruction-set Processors (ASIP).
----------------
Specialties:
----------------
* Physical Design Implementation.
* SoC Integration.
* Hands-on Experience on multiple nodes - 28nm, 40/45nm, 65nm, 90nm, 130nm.
---------------------------------------
Presentations (Public Domain)
---------------------------------------
Mots-clés
devanshu
vlsi
management
pmc sierra
physical design
semiconductor
nxp
soc
bangalore
bangalore metro
rfid
mifare
smart cards
storage
sas
san
networking
talus
icc
magma
cadence
soc encounter
synopsys
atoptech
bits pilani
architecture
philips
hdtv ic
asic
license servers
ic design project management
semiconductors
perl
p&r
ic physical design
de bono
google
six hats
technical
resource
technical management
project management
one minute management
time management
Tout plus