1) As demand for semiconductors increases, engineers face challenges to do more with less time, money, and resources. 2) ASIC companies leverage technologies like mobility, IoT, computing and networking to help reduce product development times from over a year to just 5 months. 3) Faster time-to-market allows companies to beat competitors to market, lower overall product costs, and optimize design and manufacturing cycles.

1. End-to-End Solution in
ASIC Design for Shorter TTM
Demand of Semiconductor in the Market
As the demand graph of Semiconductor goes high, engineers, hardware designers, and companies face following challenges:
“To do more with Less Time, Less Money and Less People”
Growth of Selected Markets, 17-Q2
Q2-16toQ2-17Growth
$300 billion,
Worldwide
320
340
360
380
400
2015
2016
2017
2018
2019
2020
Chip market to post 3.3%
annual growth
The global semiconductor market
will increase an average of 3.3 per
cent per year through 2020 when
the market will total more than
$400 billion
Growth of Semiconductor in Different Markets
Challenges Faced by Engineers in the Semiconductor Industry
-10%
0%
10%
20%
30%
40%
50%
60%
70%
80%
AutoADAS
AutoOther
Infotainment
Power/Body
OtherComs
Video
DC
PC
Gaming
Smartphone
Mobile
OtherCons
IndIoT
OtherInd
Automobile ConsumerCommunication Computing Industrial
65.9% 64.1%
52.8%
26.1% 25.8%
32.0%
36.0% 34.7%
20.0%
16.5%
5.7% 8.0%
3.9%
-8.8%
Tools and
MethodologiesIPQualityPower
1
2
3As the demand graph of Semiconductor goes high, engineers, hardware designers, and companies face following challenges:
Cost Capacity PerformanceTime to
Market
Customer Base
12 Months
5 Months
Revenue Market Penetration
Solutions Leveraged by ASIC Companies for Faster TTM
During competitive situations, ASIC companies leverage Mobility, IoT, Computing, and Networking to launch their products on time.
Mobility
helps
ASIC cycles
to shrink
from to
}
4During competitive situations, ASIC companies leverage Mobility, IoT, Computing, and Networking to launch their products on time.
Benefits of Faster TTM with Continuous Performance Improvement Program
Helps beat the competitors
in market
Delivers high impact on overall cost
of the product
Optimizes the time by reducing design
and manufacturing cycle
5
References :
hhp://www.electronics-sourcing.com/2017/01/12/semiconductor-market-will-recover-2017/
hhp://engagement-group.com/en/growth-charts/
hhps://www.design-reuse.com/arrcles/4360/fpga-to-asic-strategy-for-communicaaon-soc-designs.html
hhp://www.skillpad.com/how-to-reduce--me-to-market-and-improve-produccvity-through-the-use-of-elearning/
hhps://www.einfochips.com
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Talk to Us at +1-408-496-1882 or write to markeeng@einfochips.com
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15%
2%
11%
15%
6%
24%
27%
130nm
180nm
65nm
90nm
28nm
16nm
45nm
6
How eInfochips Delivers Faster TTM in the Era of Miniaturization
ASIC Design / Physical Design Services
Chip-top planning / partitioning
Block level Floorplan
Placement, Power plan & Time budgeting
Routing / Clock tree synthesis
Feedback to full chip owner for die-size closure
SignoSignoff using PTSI, Calibre, LEC, Apache tools
1.
2.
3.
DFT Architecture and Implementation
DFT Evaluation and Assessment
DFT Architecture and Methodology Development
DFT Automation
Design vs Test Time & DFT Trade-offs
ATPG Library Generation
Multiple Silicon Tape-outs Achieved
DFT Architecture Expertise
Turnkey Services RTL to GDSII
Implementation + DFT:
Synthesis, Floorplan, and Placement
Optimization, CTS, and Routing for block
Active role in feedback to oorplan team and RTL team
Provide feedback to full chip owner
TTiming closure, Crosstalk Analysis & OCV Analysis through PTSI, Physical Veriication
DFT Architecture, Scan, ATPG, BIST, Silicon Debug
28nm
45nm
65nm
90nm
130nm
20%
40%
5%15%
20%