TMPA910CRAXBG 32-Bit Display MCU
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Introduction of the features of the TMPA910CRAXBG display microcontroller
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TMPA910CRAXBG 32-Bit Display MCU
- 9. UART
Editor's Notes
- Welcome to the training module on Toshiba TMPA910CRAXBG 32-Bit Display MCU. This training module introduces the features of the TMPA910CRAXBG display microcontroller.
- LCDs have been increasingly integrated into different electronic applications to enhance the man machine interface (MMI). These applications include automotive infotainment and navigation systems, industrial control and security systems, portable test and monitoring system, and electronics products, etc. Toshibaâs TX09 series MCUs integrated LCD controller with numerous other peripherals to bring feature-rich processing solution to these applications. The TMPA910CRAXBG MCU is one member in TX09 series. Based on an ARM926EJ-S CPU operating at up to 200 MHz, the TMPA910CRAXBG features a built-in LCD controller with support for TFT and STN display resolutions up to 1024 by 768 pixels and an LCD data processor that provides image scaling, filtering and blending functions and offers real-time video processing. The TMPA910CRAXBG MCU also integrates a CMOS image sensor interface to simplify implementation of an image capture function in embedded devices. Additionally, a touch screen interface further reduces the external component count by integrating support for a man-to-machine interface. The TMPA910CRAXBG MCU utilizes a 7-layer multibus architecture so both code and data can be transferred quickly and efficiently and integrates an SD memory host controller to support high-speed mode for interaction with SD memory cards.
- The TMPA910CRAXBG microcontroller features a powerful ARM926EJ-S processor, an LCD controller and LCD Data processor, and a variety of functionality and connectivity solutions, such as SPI, UART, I 2 C, USB, a melody/alarm generator, RTC and a power management circuit. The MCU offers 56 Kbytes of RAM for program, data and display memory, an SDR and DDR SDRAM memory controller, NAND flash interface, JTAG interface, and a high-speed (480 Mbps) USB device controller.
- The TMPA910CRA has a built-in 32-bit RISC processor ARM926EJ-S manufactured by ARM. The block diagram of the ARM926EJ-S core is shown. The ARM926EJ-STM fully synthesizable processor features a enhanced 32-bit RISC CPU, flexible size instruction and data caches, and memory management unit (MMU). It also provides separate instruction and data AMBA  interfaces particularly suitable for Multi-layer AHB based systems. The ARM926EJ-S processor implements the ARMv5TEJ instruction set and includes an enhanced 16 x 32-bit multiplier, capable of single cycle MAC operations. However, the supported hardware of the TMPA910CRA core is different from that of the original ARM926EJ-S. The TMPA910CRA core does not support Coprocessor Interface, Embedded ICE-RT, TCM Interface, and ETM9 Interface.
- The TMPA910CRA has two operation modes: external memory activation mode and internal boot ROM activation mode. An operation mode is selected in accordance with the AM1 and AM0 pin status when RESETn is asserted. When it operates in external memory mode, the CPU fetches instructions from external memory and executes them after reset. When it works in BOOT mode, the CPU fetches instructions from the internal boot ROM and executes them. The internal boot ROM transfers a user program to the internal RAM via USB communication, and then branches the program into the internal RAM.
- The TMPA910CRA supports twenty eight interrupt sources. Thirty two levels of fixed hardware priority are assigned to the interrupt sources, which is used if multiple interrupt requests of the same software priority level occur simultaneously. In Interrupt Control, FIQ (Fast Interrupt Request) and IRQ (Interrupt Request) are available. Only a single FIQ source at a time is generally used in a system, to provide a true low-latency interrupt. The priority level of FIQ is most high. If multiple interrupt requests of the same software priority level occur simultaneously, the hardware priority is used to determine the interrupt to be generated. The hardware priority is assigned according to interrupt source numbers: interrupt source number 0 has the highest priority and interrupt source number 31 has the lowest priority.
- The TMPA910CRA contains six channels of 16-bit timers. Each timer has the same register sets of the same operation. When a value is written in the timer load register, the value is loaded and is counted down to 0 when counting is enabled. They operate in the following four modes: free-running mode, periodic timer mode, one-shot timer mode, and PWM mode.
- The TMPA910CRA contains two UART channels. Each channel has a baud rate generator, transmit FIFO, receive FIFO, transmit logic, receive logic, and interrupt generation logic. The baud rate generator controls the timing of UART Transmit and Receive. CPU data written across the APB interface is stored in the transmit FIFO until read out by the transmit logic. Received data and corresponding error bits are stored in the receive FIFO by the receive logic until read out by the CPU across the APB interface. The transmit logic performs parallel-to-serial conversion on the data read from the transmit FIFO. The receive logic performs serial-to-parallel conversion on the received bit stream after a start bit has been detected. Individual maskable active HIGH interrupts are generated by interrupt generation logic.
- The I 2 C module contains two channels. This module operates as a master or slave device on the I 2 C bus. The master device drives the serial clock line (SCL) of the bus, sends 8-bit addresses, and sends or receives data of 1 to 8 bits. The slave device sends 8-bit addresses and sends or receives serial data of 1 to 8 bits in synchronization with the serial clock on the bus. The device that operates as a receiver can output an acknowledge signal after reception of serial data and the device that operates as a transmitter can receive that acknowledge signal, regardless of whether the device is a master or slave. In multimaster mode in which multiple masters exist on the same bus, serial clock synchronization and arbitration lost to maintain consistency of serial data are supported.
- The TMPA910CRA contains the SSP comprised of two channels, which operate identically. The SSP is an interface for serial communication with peripheral devices that have three types of synchronous serial interfaces. The SSP performs serial-to-parallel conversion on data received from a peripheral device. The transmit and receive paths are buffered with a 16-bit wide, 8 locations deep independent transmit FIFO and receive FIFO in transmit mode and receive mode, respectively. The SSP contains a programmable prescaler to generate the serial output clock (SP0SLK) from the input clock (PCLK). The TMPA910CRA contains a serial input/output circuit compliant with the I2S format. By connecting an external audio LSI, such as an AD converter or DA converter, the I 2 S interface can support the implementation of a digital audio system. The I2S circuit contains two channels and each channel can be controlled and operated independently.
- The USB device controller consists of the core part called UDC2 and the bus bridge part called UDC2AB which enables connection with the AHB bus. UDC2 is a core which controls connection of USB functions to the Universal Serial Bus. UDC2 automatically processes the USB protocol and its PHY-end interface can be accessed via UTMI. UDC2AB is the bridge circuit between Toshiba USB-Spec2.0 Device Controller (hereinafter âUDC2â) and AHB. UDC2AB has the DMA controller that supports the AHB master transfer and controls transfer between the specified address on AHB and the Endpoint-FIFO (Endpoint I/F) inside UDC2.
- The TMPA910CRA incorporates a color-capable LCD controller. This LCD controller module contains an AHB master and slave interface, DMA FIFO and related control logic, a pixel serializer, RAM palette, gray scaler, panel clock generator, timing controller, and interrupt control. The AMBA_AHB master interface reads display data from a selected slave (memory) and transfer it to CLCDC_DMA_FIFO. The CPU reads and writes control registers and the palette RAM to control the CLCDC through the AMBA_AHB slave interface. In order to match single and dual panel LCD types, display data read from the display RAM is buffered into the two DMA FIFOs that can control the data individually. The Pixel Serializer reads 32-bit LCD data from the DMA FIFO and converts it into 24-, 16-, 8-, 4-, 2-, or 1-bit data according to the operation mode. Pixel data is replaced into data of 16 bits RAM palette and then output. The gray algorithm supports monochrome display 15 gray scale levels. Panel Clock Generator can set the frequency division rate of data transfer clock (LCLCP) used in the internal clock (HCLK) and LCDC.
- This microcontroller incorporates the LCD Data Process Accelerator function (LCDDA) asan auxiliary function for display. The LCDDA supports the scaler function that scales up/down display data including the filter (Bi-Cubic method) processing, and the image rotation function that rotates and mirror-inverts display data function, as well as the function of superimposing two pictures (Gray level adjustment: α Blend, Inserting picture into picture: Picture in Picture, Superimposing text: Font Draw)
- The scaler function of the LCDDA can insert interpolation data of 255 points at maximum between original pixels using the Bi-Cubic method. To use the scaler function, original image data (RGB) needs to have been written into the dedicated Dual Port RAM. The scaler function supports the function of correcting sampling points for scaling up/down processing. Using this function can express more natural pictures. The BLEND processing of the LCDDA first breaks each data of two pictures into the basis of pixels and then breaks them into the basis of RGB. The FONT function is the function of overwriting data defined in monochrome onto a color picture. To perform rotation, the rotation process calculates addresses when the LCDDA reads and copies back original pictures.
- An interface for 4-terminal resistor network touch-screen is built in. The TSI easily supports two procedures: touch detection and X/Y position measurement. Each procedure is performed by setting the TSI control register (TSICR0 and TSICR1) and using an internal AD converter. The touch detection procedure includes the procedures starting from when the pen is touched onto the touch screen and until the pen-touch is detected. After an X/Y position measuring at INTA interrupt routine, and an X/Y position measuring procedure is terminated, return to this procedure to wait for the next touch.
- The CMSI captures data sent from a CMOS image sensor in synchronization with the CMSPCK clock. When the downscaling or trimming function is used, only required pixel data is captured according to the specified setting. Next, when color-converting YUV422 into RGB, color space conversion is performed at the point when a pixel of YUV data has been captured, and then the converted RGB data is stored in the FIFO one after another. At the point when the FIFO contains data with a specified number of bytes, INTCMSF is output. This INTCMSF can be used as a trigger to start DMA data transfer.
- The MCU includes Real-Time Clock, Melody and Alarm generator block. The melody block can generate melody waveforms at any frequency from 4Hz to 5461Hz. The alarm block can generate 8 patterns of alarm output and 5 types of fixed-interval interrupts. By connecting buzzer etc outside, alarm and melody sounds can easily be played. The real-time clock (32bit counter) can count every second based on the frequency divided from the low-speed clock. By comparing the count value with the value set in the RTCCOMP register, an interrupt can be generated.
- The start kit provides reference platform and software support for simplified development of industrial and consumer applications. It brings together all of the hardware and software needed to develop and test applications based on the TMPA910CRAXBG. The Starter Kitâs hardware development PCB measures just 110mm x 150mm. In addition to the TMPA910CRAXBG processor, onboard functionality includes a 3.5-inch display with a touch screen, Ethernet connectivity, a 480Mbps USB 2.0 interface and an RS232 connector. An audio DAC, connected to the processor I 2 S bus, provides the ability to output excellent sound quality, while board memory comprises 512MBit SDRAM, 256Mbit NOR Flash and 2Gbit NAND Flash. An SD card socket facilitates the use of portable storage.
- Thank you for taking the time to view this presentation on â TMPA910CRAXBG 32-Bit Display MCUâ . If you would like to learn more or go on to purchase some of these devices, you may either click on the part list link, or simply call our sales hotline. For more technical information you may either visit the TOSHIBA site â link shown â or if you would prefer to speak to someone live, please call our hotline number, or even use our âlive chatâ online facility.