SlideShare une entreprise Scribd logo
1  sur  24
THE DECODER
PREPARED BY: JOHN LEXTER L. EMBERADOR
         BSIE-201 ELECTRONICS
  SUBMITTED TO: MS. JANICE G. DULCE
   DATE SUBMITTED: AUGUST 13,2012
BASIC CONCEPT
1. A DECODER circuit is used to recognize the
  various combinations of an input word and
  provide an output for each combination.
2.If an input word contains N “bits” then the
  decoder can have 2N outputs.
3.A combination of gates can be used to
  construct a decoder circuit.
4.A BCD to Decimal Decoder is used to provide
  decimal information from a binary coded
  input.
INTRODUCTORY INFORMATION
● A decoder can be thought of in the
  opposite sense as an encoder. In
  encoder, the decimal number was coded
  so that digital operation could be
  performed using binary numbers. The
  binary information which was processed
  in a coded form by digital circuits can be
  recognized or decoded by a decoder
  circuit.
• The resulting outputs will represent
  the original input code. A typical
  example of this is a BCD to Decimal
  Decoder.
• Table 6-1 shows the decimal
  equivalents of a four “bit” binary
  word. In addition it shows the states
  of the four inputs ABCD to a decider
  required to represent decimal
  numbers 0 through 9.
• Notice that the table shows a four bit binary
  word can produce up to 16 distinct outputs. A
  general rule for decoders is that when the
  number of inputs is equal to a number N, the
  decoder will produce 2N outputs.
• For table 6-1, N equals 4 and there will be 24
  or 16 outputs. However, we need only to
  produce one digit of a decimal number or the
  decimal symbols 0 through 9.
• Figure 6-1 shows a typical application for a
  BCD to Decimal decoder.
• The functions shown will provide a
  two digit numeric readout using
  Nixie ® tubes as display devices.
• The requirement is to provide a
  signal to energize the proper
  number, 0 through 9 of the Nixie
  Tube, when a certain number of
  input pulses are counted in Binary
  Coded Decimal form.
• That is, a four bit BCD word exist as inputs to
  the decoder and outputs 0 through 9 are
  required for Nixie tube drivers. The circuitry
  for a second digit is shown in block form, is
  identical to the first digit and accepts a pulse
  following each 0 through 9 sequence of the
  first digit.
• Simultaneously, a reset pulse within the
  counter will initiate the BCD code 0000 and
  the numeric 0 output. The system shown
  represents a two digit counter that will count
  up to 99 and then reset to 0.
IDENTIFYING BCD TO
     DECIMAL DECODER
• A BCD to Decimal Decoder circuit
  is shown in Figure 6-2.
• As we can see from the figure 6-1 and
  table 6-1, the decoding process
  essentially requires the logic AND
  operation. The table and figure show the
  BCD inputs required to produce the
  decimal outputs 0 through 9.
• Recalling that all HI logic states are
  required to produce HI outputs, notice
  that the circuit shows inverters to
  provide HI inputs at the AND gates when
  BCD inputs A,B,C and D are L0 (A̅,B̅,C̅ and
  D̅).
• Also notice that all lines of the circuit are identified
  showing the input state and code place value for
  each input bit. For example, if the BCD code for the
  number 6 were to be decoded the input from table
  6-1 would be 0110 or D̅CBA̅. In figure 6-2 a L0 at the
  input to INVERTERS (D) and (A)(circles) will produce
  a HI at these outputs (no circles). The remaining 2
  input bits required to produce a HI output from AND
  gate (6), namely C and B are HI and will activate the
  gate without inversion. Looking at the input lines to
  gate (6) will verify that a HI will exist on all inputs for
  the code 0110 or D̅CBA̅ with place values (8̅421̅).
• All remaining gates of figure 6-
  2 can be analyzed in the same
  manner. A HI at the outputs
  would provide the signal
  required to activate a numeric
  readout.
ANALYZING TROUBLE SYMPTOMS OF
 DECODER CIRCUIT AND ITS SIGNAL
• Decoder circuit operation can be checked by
  noting the inputs and outputs. An analysis of
  the inputs and outputs usually indicates
  location of the circuit fault. Then, logic probe
  circuit tracing can be employed to isolate the
  exact location of the fault.
• For example, in the BCD decoder circuit of
  figure 6-3, a defective gate will affect only one
  decimal output, the gate might be open or
  shorted, in which case the output would
  remain permanently L0 or HI.
• On the other hand, if one of the
  INVERTERS were defective, the
  decimal outputs would be incorrect
  for several inputs. If the C̅ inverter
  were in a permanently HI state, for
  example, then as the BCD inputs
  proceeded through a count from 000
  to 111, we would get the outputs
  shown in table 6-3.
POST-TEST
I.IDENTIFICATION
1.A DECODER can be thought of in the
  opposite sense as an __________.
2.What is the general rule for decoder, if
  the number of the inputs is equal to a
  number N, the decoder will produce
  _________ outputs.
3.__________ is used to provide decimal
  information from a binary coded input.
4.In the figure 6-1 and table 6-1, the decoding
   process essentially requires what kind of logic
   operation?
5.If one of the INVERTERS were defective, what
   would happened to the decimal output of a
   decoder circuit?
II. Rewrite the following Input Binary Code into
   Digital Logic State.
1.0100
2.1001
3.0011
4.1100
5.1010
III. Give the Output Decimal Number of the
   following Digital Logic State.
1.DC̅BA
2.D̅CBA̅
3.D̅C̅B̅A
4.DC̅BA̅
5.DCB̅A
IV. Give the Output Decoder of the following
   Inputs in the general rule 2N.
1.N=3
2.N=5
3.N=8
4.N=10
5.N=12
KEY ANSWERS
I.
1.ENCODER
2.2N
3.BCD TO DECIMAL DECODER
4.AND OPERATION
5.INCORRECT FOR SEVERAL INPUTS
II.
1.D̅CB̅A̅
2.DC̅B̅A
3.D̅C̅BA
4.DCB̅A̅
5.DC̅BA̅
KEY ANSWERS
III.
1.11
2.6
3.1
4.10
5.13
IV.
1.23 = 8
2.25 =32
3.28 =256
4.210 =1024
5.212 =4096

Contenu connexe

Tendances

Tendances (20)

decorder and encoder and its applications
decorder and encoder and its applicationsdecorder and encoder and its applications
decorder and encoder and its applications
 
Encoders
EncodersEncoders
Encoders
 
Decoder
DecoderDecoder
Decoder
 
Multiplexer
MultiplexerMultiplexer
Multiplexer
 
Types of encoders and decoders with truth tables
Types of encoders and decoders with truth tablesTypes of encoders and decoders with truth tables
Types of encoders and decoders with truth tables
 
Decoder
DecoderDecoder
Decoder
 
Encoders and decoders
Encoders and decodersEncoders and decoders
Encoders and decoders
 
Decoders
DecodersDecoders
Decoders
 
Encoder & Decoder
Encoder & DecoderEncoder & Decoder
Encoder & Decoder
 
Encoders
EncodersEncoders
Encoders
 
Encoders
EncodersEncoders
Encoders
 
Digital logic design DLD Logic gates
Digital logic design DLD Logic gatesDigital logic design DLD Logic gates
Digital logic design DLD Logic gates
 
Digital logic gates
Digital logic gatesDigital logic gates
Digital logic gates
 
Combinational circuit
Combinational circuitCombinational circuit
Combinational circuit
 
Encoder and decoder
Encoder and decoderEncoder and decoder
Encoder and decoder
 
COMPUTER ORGANIZATION -Multiplexer,Demultiplexer, Encoder
COMPUTER ORGANIZATION -Multiplexer,Demultiplexer, EncoderCOMPUTER ORGANIZATION -Multiplexer,Demultiplexer, Encoder
COMPUTER ORGANIZATION -Multiplexer,Demultiplexer, Encoder
 
decoder and encoder
 decoder and encoder decoder and encoder
decoder and encoder
 
Saur lecture 16
Saur lecture 16Saur lecture 16
Saur lecture 16
 
Digital Logic circuit
Digital Logic circuitDigital Logic circuit
Digital Logic circuit
 
multiplexer and d-multiplexer
multiplexer and d-multiplexermultiplexer and d-multiplexer
multiplexer and d-multiplexer
 

En vedette

Decoder for digital electronics
Decoder for digital electronicsDecoder for digital electronics
Decoder for digital electronicsKamil Hussain
 
Ceng232 Decoder Multiplexer Adder
Ceng232 Decoder Multiplexer AdderCeng232 Decoder Multiplexer Adder
Ceng232 Decoder Multiplexer Addergueste731a4
 
Real-time Implementation of Sphere Decoder-based MIMO Wireless System (EUSIPC...
Real-time Implementation of Sphere Decoder-based MIMO Wireless System (EUSIPC...Real-time Implementation of Sphere Decoder-based MIMO Wireless System (EUSIPC...
Real-time Implementation of Sphere Decoder-based MIMO Wireless System (EUSIPC...TSC University of Mondragon
 
Half Subtractor : Combiational Circuit
Half Subtractor : Combiational CircuitHalf Subtractor : Combiational Circuit
Half Subtractor : Combiational CircuitDoCircuits
 
RSA NetWitness Log Decoder
RSA NetWitness Log DecoderRSA NetWitness Log Decoder
RSA NetWitness Log DecoderSusam Pal
 
logical circuits substractors
logical circuits substractors logical circuits substractors
logical circuits substractors Fâhém Ähmêd
 
Encoders and Decoders
Encoders and DecodersEncoders and Decoders
Encoders and DecodersNic JM
 
B sc cs i bo-de u-iii counters & registers
B sc cs i bo-de u-iii counters & registersB sc cs i bo-de u-iii counters & registers
B sc cs i bo-de u-iii counters & registersRai University
 
Design half ,full Adder and Subtractor
Design half ,full Adder and SubtractorDesign half ,full Adder and Subtractor
Design half ,full Adder and SubtractorJaimin@prt.ltd.
 

En vedette (11)

Decoder for digital electronics
Decoder for digital electronicsDecoder for digital electronics
Decoder for digital electronics
 
Ceng232 Decoder Multiplexer Adder
Ceng232 Decoder Multiplexer AdderCeng232 Decoder Multiplexer Adder
Ceng232 Decoder Multiplexer Adder
 
Real-time Implementation of Sphere Decoder-based MIMO Wireless System (EUSIPC...
Real-time Implementation of Sphere Decoder-based MIMO Wireless System (EUSIPC...Real-time Implementation of Sphere Decoder-based MIMO Wireless System (EUSIPC...
Real-time Implementation of Sphere Decoder-based MIMO Wireless System (EUSIPC...
 
Half subtracter
Half subtracterHalf subtracter
Half subtracter
 
Half Subtractor : Combiational Circuit
Half Subtractor : Combiational CircuitHalf Subtractor : Combiational Circuit
Half Subtractor : Combiational Circuit
 
RSA NetWitness Log Decoder
RSA NetWitness Log DecoderRSA NetWitness Log Decoder
RSA NetWitness Log Decoder
 
logical circuits substractors
logical circuits substractors logical circuits substractors
logical circuits substractors
 
Encoders and Decoders
Encoders and DecodersEncoders and Decoders
Encoders and Decoders
 
B sc cs i bo-de u-iii counters & registers
B sc cs i bo-de u-iii counters & registersB sc cs i bo-de u-iii counters & registers
B sc cs i bo-de u-iii counters & registers
 
Encoder and decoder
Encoder and decoderEncoder and decoder
Encoder and decoder
 
Design half ,full Adder and Subtractor
Design half ,full Adder and SubtractorDesign half ,full Adder and Subtractor
Design half ,full Adder and Subtractor
 

Similaire à The decoder

Encoder-and-decoder.pptx
Encoder-and-decoder.pptxEncoder-and-decoder.pptx
Encoder-and-decoder.pptxKamranAli649587
 
decoders121-170714184489769876987698749.pptx
decoders121-170714184489769876987698749.pptxdecoders121-170714184489769876987698749.pptx
decoders121-170714184489769876987698749.pptxtlap4412
 
Decoders-Digital Electronics
Decoders-Digital ElectronicsDecoders-Digital Electronics
Decoders-Digital ElectronicsPaurav Shah
 
Unit 4 combinational circuit
Unit 4 combinational circuitUnit 4 combinational circuit
Unit 4 combinational circuitKalai Selvi
 
Project Report On 0-9 decade counter
Project Report On 0-9 decade counterProject Report On 0-9 decade counter
Project Report On 0-9 decade counterOmkar Rane
 
Chapter 5: Cominational Logic with MSI and LSI
Chapter 5: Cominational Logic with MSI and LSIChapter 5: Cominational Logic with MSI and LSI
Chapter 5: Cominational Logic with MSI and LSIEr. Nawaraj Bhandari
 
FYBSC IT Digital Electronics Unit III Chapter I Combinational Logic Circuits
FYBSC IT Digital Electronics Unit III Chapter I Combinational Logic CircuitsFYBSC IT Digital Electronics Unit III Chapter I Combinational Logic Circuits
FYBSC IT Digital Electronics Unit III Chapter I Combinational Logic CircuitsArti Parab Academics
 
I semester Unit 4 combinational circuits.pptx
I semester Unit 4 combinational circuits.pptxI semester Unit 4 combinational circuits.pptx
I semester Unit 4 combinational circuits.pptxMayank Pandey
 
Binary to gray converter using xor
Binary to gray converter using xor Binary to gray converter using xor
Binary to gray converter using xor DINESH DEVIREDDY
 
combinational-circuit (1).ppt
combinational-circuit (1).pptcombinational-circuit (1).ppt
combinational-circuit (1).pptThanmayiKumar
 
4,encoder & decoder MUX and DEMUX EEng - Copy.pdf
4,encoder & decoder MUX and DEMUX EEng - Copy.pdf4,encoder & decoder MUX and DEMUX EEng - Copy.pdf
4,encoder & decoder MUX and DEMUX EEng - Copy.pdfDamotTesfaye
 
Comparators_and_Code_Convertersv.pptx.ppt
Comparators_and_Code_Convertersv.pptx.pptComparators_and_Code_Convertersv.pptx.ppt
Comparators_and_Code_Convertersv.pptx.pptHardikGupta400524
 
Digital electronices encode decode
Digital electronices encode decodeDigital electronices encode decode
Digital electronices encode decodeSabbir Ahmed Zoy
 

Similaire à The decoder (20)

Encoder-and-decoder.pptx
Encoder-and-decoder.pptxEncoder-and-decoder.pptx
Encoder-and-decoder.pptx
 
STLD-Combinational logic design
STLD-Combinational  logic design STLD-Combinational  logic design
STLD-Combinational logic design
 
B sc3 unit 4 combi..lckt
B sc3 unit 4 combi..lcktB sc3 unit 4 combi..lckt
B sc3 unit 4 combi..lckt
 
decoders121-170714184489769876987698749.pptx
decoders121-170714184489769876987698749.pptxdecoders121-170714184489769876987698749.pptx
decoders121-170714184489769876987698749.pptx
 
Decoders-Digital Electronics
Decoders-Digital ElectronicsDecoders-Digital Electronics
Decoders-Digital Electronics
 
Unit 4 combinational circuit
Unit 4 combinational circuitUnit 4 combinational circuit
Unit 4 combinational circuit
 
Project Report On 0-9 decade counter
Project Report On 0-9 decade counterProject Report On 0-9 decade counter
Project Report On 0-9 decade counter
 
Chapter 5: Cominational Logic with MSI and LSI
Chapter 5: Cominational Logic with MSI and LSIChapter 5: Cominational Logic with MSI and LSI
Chapter 5: Cominational Logic with MSI and LSI
 
FYBSC IT Digital Electronics Unit III Chapter I Combinational Logic Circuits
FYBSC IT Digital Electronics Unit III Chapter I Combinational Logic CircuitsFYBSC IT Digital Electronics Unit III Chapter I Combinational Logic Circuits
FYBSC IT Digital Electronics Unit III Chapter I Combinational Logic Circuits
 
Chapter-04.pdf
Chapter-04.pdfChapter-04.pdf
Chapter-04.pdf
 
I semester Unit 4 combinational circuits.pptx
I semester Unit 4 combinational circuits.pptxI semester Unit 4 combinational circuits.pptx
I semester Unit 4 combinational circuits.pptx
 
BCDCONVERTER.pptx
BCDCONVERTER.pptxBCDCONVERTER.pptx
BCDCONVERTER.pptx
 
Binary to gray converter using xor
Binary to gray converter using xor Binary to gray converter using xor
Binary to gray converter using xor
 
combinational-circuit (1).ppt
combinational-circuit (1).pptcombinational-circuit (1).ppt
combinational-circuit (1).ppt
 
Logic gates
Logic gatesLogic gates
Logic gates
 
DCF-Combinational circuit
DCF-Combinational circuitDCF-Combinational circuit
DCF-Combinational circuit
 
4,encoder & decoder MUX and DEMUX EEng - Copy.pdf
4,encoder & decoder MUX and DEMUX EEng - Copy.pdf4,encoder & decoder MUX and DEMUX EEng - Copy.pdf
4,encoder & decoder MUX and DEMUX EEng - Copy.pdf
 
Comparators_and_Code_Convertersv.pptx.ppt
Comparators_and_Code_Convertersv.pptx.pptComparators_and_Code_Convertersv.pptx.ppt
Comparators_and_Code_Convertersv.pptx.ppt
 
ATT SMK.pptx
ATT SMK.pptxATT SMK.pptx
ATT SMK.pptx
 
Digital electronices encode decode
Digital electronices encode decodeDigital electronices encode decode
Digital electronices encode decode
 

Plus de john lexter emberador (9)

BASIC LOGIC GATES.pdf
BASIC LOGIC GATES.pdfBASIC LOGIC GATES.pdf
BASIC LOGIC GATES.pdf
 
Analog Multimeter.pdf
Analog Multimeter.pdfAnalog Multimeter.pdf
Analog Multimeter.pdf
 
About anthropology
About anthropologyAbout anthropology
About anthropology
 
18019469 history-as-a-discipline
18019469 history-as-a-discipline18019469 history-as-a-discipline
18019469 history-as-a-discipline
 
Presentation1
Presentation1Presentation1
Presentation1
 
J. parallel (synchronous) counters
J. parallel (synchronous) countersJ. parallel (synchronous) counters
J. parallel (synchronous) counters
 
J. parallel (synchronous) counters
J. parallel (synchronous) countersJ. parallel (synchronous) counters
J. parallel (synchronous) counters
 
G. ripple counter
G. ripple counterG. ripple counter
G. ripple counter
 
Adays wait
Adays waitAdays wait
Adays wait
 

Dernier

TeamStation AI System Report LATAM IT Salaries 2024
TeamStation AI System Report LATAM IT Salaries 2024TeamStation AI System Report LATAM IT Salaries 2024
TeamStation AI System Report LATAM IT Salaries 2024Lonnie McRorey
 
SIP trunking in Janus @ Kamailio World 2024
SIP trunking in Janus @ Kamailio World 2024SIP trunking in Janus @ Kamailio World 2024
SIP trunking in Janus @ Kamailio World 2024Lorenzo Miniero
 
Transcript: New from BookNet Canada for 2024: Loan Stars - Tech Forum 2024
Transcript: New from BookNet Canada for 2024: Loan Stars - Tech Forum 2024Transcript: New from BookNet Canada for 2024: Loan Stars - Tech Forum 2024
Transcript: New from BookNet Canada for 2024: Loan Stars - Tech Forum 2024BookNet Canada
 
Passkey Providers and Enabling Portability: FIDO Paris Seminar.pptx
Passkey Providers and Enabling Portability: FIDO Paris Seminar.pptxPasskey Providers and Enabling Portability: FIDO Paris Seminar.pptx
Passkey Providers and Enabling Portability: FIDO Paris Seminar.pptxLoriGlavin3
 
Developer Data Modeling Mistakes: From Postgres to NoSQL
Developer Data Modeling Mistakes: From Postgres to NoSQLDeveloper Data Modeling Mistakes: From Postgres to NoSQL
Developer Data Modeling Mistakes: From Postgres to NoSQLScyllaDB
 
Use of FIDO in the Payments and Identity Landscape: FIDO Paris Seminar.pptx
Use of FIDO in the Payments and Identity Landscape: FIDO Paris Seminar.pptxUse of FIDO in the Payments and Identity Landscape: FIDO Paris Seminar.pptx
Use of FIDO in the Payments and Identity Landscape: FIDO Paris Seminar.pptxLoriGlavin3
 
Gen AI in Business - Global Trends Report 2024.pdf
Gen AI in Business - Global Trends Report 2024.pdfGen AI in Business - Global Trends Report 2024.pdf
Gen AI in Business - Global Trends Report 2024.pdfAddepto
 
A Deep Dive on Passkeys: FIDO Paris Seminar.pptx
A Deep Dive on Passkeys: FIDO Paris Seminar.pptxA Deep Dive on Passkeys: FIDO Paris Seminar.pptx
A Deep Dive on Passkeys: FIDO Paris Seminar.pptxLoriGlavin3
 
Streamlining Python Development: A Guide to a Modern Project Setup
Streamlining Python Development: A Guide to a Modern Project SetupStreamlining Python Development: A Guide to a Modern Project Setup
Streamlining Python Development: A Guide to a Modern Project SetupFlorian Wilhelm
 
DevEX - reference for building teams, processes, and platforms
DevEX - reference for building teams, processes, and platformsDevEX - reference for building teams, processes, and platforms
DevEX - reference for building teams, processes, and platformsSergiu Bodiu
 
Ensuring Technical Readiness For Copilot in Microsoft 365
Ensuring Technical Readiness For Copilot in Microsoft 365Ensuring Technical Readiness For Copilot in Microsoft 365
Ensuring Technical Readiness For Copilot in Microsoft 3652toLead Limited
 
From Family Reminiscence to Scholarly Archive .
From Family Reminiscence to Scholarly Archive .From Family Reminiscence to Scholarly Archive .
From Family Reminiscence to Scholarly Archive .Alan Dix
 
The Ultimate Guide to Choosing WordPress Pros and Cons
The Ultimate Guide to Choosing WordPress Pros and ConsThe Ultimate Guide to Choosing WordPress Pros and Cons
The Ultimate Guide to Choosing WordPress Pros and ConsPixlogix Infotech
 
Advanced Computer Architecture – An Introduction
Advanced Computer Architecture – An IntroductionAdvanced Computer Architecture – An Introduction
Advanced Computer Architecture – An IntroductionDilum Bandara
 
Hyperautomation and AI/ML: A Strategy for Digital Transformation Success.pdf
Hyperautomation and AI/ML: A Strategy for Digital Transformation Success.pdfHyperautomation and AI/ML: A Strategy for Digital Transformation Success.pdf
Hyperautomation and AI/ML: A Strategy for Digital Transformation Success.pdfPrecisely
 
WordPress Websites for Engineers: Elevate Your Brand
WordPress Websites for Engineers: Elevate Your BrandWordPress Websites for Engineers: Elevate Your Brand
WordPress Websites for Engineers: Elevate Your Brandgvaughan
 
Dev Dives: Streamline document processing with UiPath Studio Web
Dev Dives: Streamline document processing with UiPath Studio WebDev Dives: Streamline document processing with UiPath Studio Web
Dev Dives: Streamline document processing with UiPath Studio WebUiPathCommunity
 
DSPy a system for AI to Write Prompts and Do Fine Tuning
DSPy a system for AI to Write Prompts and Do Fine TuningDSPy a system for AI to Write Prompts and Do Fine Tuning
DSPy a system for AI to Write Prompts and Do Fine TuningLars Bell
 
Unraveling Multimodality with Large Language Models.pdf
Unraveling Multimodality with Large Language Models.pdfUnraveling Multimodality with Large Language Models.pdf
Unraveling Multimodality with Large Language Models.pdfAlex Barbosa Coqueiro
 
unit 4 immunoblotting technique complete.pptx
unit 4 immunoblotting technique complete.pptxunit 4 immunoblotting technique complete.pptx
unit 4 immunoblotting technique complete.pptxBkGupta21
 

Dernier (20)

TeamStation AI System Report LATAM IT Salaries 2024
TeamStation AI System Report LATAM IT Salaries 2024TeamStation AI System Report LATAM IT Salaries 2024
TeamStation AI System Report LATAM IT Salaries 2024
 
SIP trunking in Janus @ Kamailio World 2024
SIP trunking in Janus @ Kamailio World 2024SIP trunking in Janus @ Kamailio World 2024
SIP trunking in Janus @ Kamailio World 2024
 
Transcript: New from BookNet Canada for 2024: Loan Stars - Tech Forum 2024
Transcript: New from BookNet Canada for 2024: Loan Stars - Tech Forum 2024Transcript: New from BookNet Canada for 2024: Loan Stars - Tech Forum 2024
Transcript: New from BookNet Canada for 2024: Loan Stars - Tech Forum 2024
 
Passkey Providers and Enabling Portability: FIDO Paris Seminar.pptx
Passkey Providers and Enabling Portability: FIDO Paris Seminar.pptxPasskey Providers and Enabling Portability: FIDO Paris Seminar.pptx
Passkey Providers and Enabling Portability: FIDO Paris Seminar.pptx
 
Developer Data Modeling Mistakes: From Postgres to NoSQL
Developer Data Modeling Mistakes: From Postgres to NoSQLDeveloper Data Modeling Mistakes: From Postgres to NoSQL
Developer Data Modeling Mistakes: From Postgres to NoSQL
 
Use of FIDO in the Payments and Identity Landscape: FIDO Paris Seminar.pptx
Use of FIDO in the Payments and Identity Landscape: FIDO Paris Seminar.pptxUse of FIDO in the Payments and Identity Landscape: FIDO Paris Seminar.pptx
Use of FIDO in the Payments and Identity Landscape: FIDO Paris Seminar.pptx
 
Gen AI in Business - Global Trends Report 2024.pdf
Gen AI in Business - Global Trends Report 2024.pdfGen AI in Business - Global Trends Report 2024.pdf
Gen AI in Business - Global Trends Report 2024.pdf
 
A Deep Dive on Passkeys: FIDO Paris Seminar.pptx
A Deep Dive on Passkeys: FIDO Paris Seminar.pptxA Deep Dive on Passkeys: FIDO Paris Seminar.pptx
A Deep Dive on Passkeys: FIDO Paris Seminar.pptx
 
Streamlining Python Development: A Guide to a Modern Project Setup
Streamlining Python Development: A Guide to a Modern Project SetupStreamlining Python Development: A Guide to a Modern Project Setup
Streamlining Python Development: A Guide to a Modern Project Setup
 
DevEX - reference for building teams, processes, and platforms
DevEX - reference for building teams, processes, and platformsDevEX - reference for building teams, processes, and platforms
DevEX - reference for building teams, processes, and platforms
 
Ensuring Technical Readiness For Copilot in Microsoft 365
Ensuring Technical Readiness For Copilot in Microsoft 365Ensuring Technical Readiness For Copilot in Microsoft 365
Ensuring Technical Readiness For Copilot in Microsoft 365
 
From Family Reminiscence to Scholarly Archive .
From Family Reminiscence to Scholarly Archive .From Family Reminiscence to Scholarly Archive .
From Family Reminiscence to Scholarly Archive .
 
The Ultimate Guide to Choosing WordPress Pros and Cons
The Ultimate Guide to Choosing WordPress Pros and ConsThe Ultimate Guide to Choosing WordPress Pros and Cons
The Ultimate Guide to Choosing WordPress Pros and Cons
 
Advanced Computer Architecture – An Introduction
Advanced Computer Architecture – An IntroductionAdvanced Computer Architecture – An Introduction
Advanced Computer Architecture – An Introduction
 
Hyperautomation and AI/ML: A Strategy for Digital Transformation Success.pdf
Hyperautomation and AI/ML: A Strategy for Digital Transformation Success.pdfHyperautomation and AI/ML: A Strategy for Digital Transformation Success.pdf
Hyperautomation and AI/ML: A Strategy for Digital Transformation Success.pdf
 
WordPress Websites for Engineers: Elevate Your Brand
WordPress Websites for Engineers: Elevate Your BrandWordPress Websites for Engineers: Elevate Your Brand
WordPress Websites for Engineers: Elevate Your Brand
 
Dev Dives: Streamline document processing with UiPath Studio Web
Dev Dives: Streamline document processing with UiPath Studio WebDev Dives: Streamline document processing with UiPath Studio Web
Dev Dives: Streamline document processing with UiPath Studio Web
 
DSPy a system for AI to Write Prompts and Do Fine Tuning
DSPy a system for AI to Write Prompts and Do Fine TuningDSPy a system for AI to Write Prompts and Do Fine Tuning
DSPy a system for AI to Write Prompts and Do Fine Tuning
 
Unraveling Multimodality with Large Language Models.pdf
Unraveling Multimodality with Large Language Models.pdfUnraveling Multimodality with Large Language Models.pdf
Unraveling Multimodality with Large Language Models.pdf
 
unit 4 immunoblotting technique complete.pptx
unit 4 immunoblotting technique complete.pptxunit 4 immunoblotting technique complete.pptx
unit 4 immunoblotting technique complete.pptx
 

The decoder

  • 1. THE DECODER PREPARED BY: JOHN LEXTER L. EMBERADOR BSIE-201 ELECTRONICS SUBMITTED TO: MS. JANICE G. DULCE DATE SUBMITTED: AUGUST 13,2012
  • 2. BASIC CONCEPT 1. A DECODER circuit is used to recognize the various combinations of an input word and provide an output for each combination. 2.If an input word contains N “bits” then the decoder can have 2N outputs. 3.A combination of gates can be used to construct a decoder circuit. 4.A BCD to Decimal Decoder is used to provide decimal information from a binary coded input.
  • 3. INTRODUCTORY INFORMATION ● A decoder can be thought of in the opposite sense as an encoder. In encoder, the decimal number was coded so that digital operation could be performed using binary numbers. The binary information which was processed in a coded form by digital circuits can be recognized or decoded by a decoder circuit.
  • 4. • The resulting outputs will represent the original input code. A typical example of this is a BCD to Decimal Decoder. • Table 6-1 shows the decimal equivalents of a four “bit” binary word. In addition it shows the states of the four inputs ABCD to a decider required to represent decimal numbers 0 through 9.
  • 5.
  • 6. • Notice that the table shows a four bit binary word can produce up to 16 distinct outputs. A general rule for decoders is that when the number of inputs is equal to a number N, the decoder will produce 2N outputs. • For table 6-1, N equals 4 and there will be 24 or 16 outputs. However, we need only to produce one digit of a decimal number or the decimal symbols 0 through 9. • Figure 6-1 shows a typical application for a BCD to Decimal decoder.
  • 7.
  • 8. • The functions shown will provide a two digit numeric readout using Nixie ® tubes as display devices. • The requirement is to provide a signal to energize the proper number, 0 through 9 of the Nixie Tube, when a certain number of input pulses are counted in Binary Coded Decimal form.
  • 9.
  • 10. • That is, a four bit BCD word exist as inputs to the decoder and outputs 0 through 9 are required for Nixie tube drivers. The circuitry for a second digit is shown in block form, is identical to the first digit and accepts a pulse following each 0 through 9 sequence of the first digit. • Simultaneously, a reset pulse within the counter will initiate the BCD code 0000 and the numeric 0 output. The system shown represents a two digit counter that will count up to 99 and then reset to 0.
  • 11. IDENTIFYING BCD TO DECIMAL DECODER • A BCD to Decimal Decoder circuit is shown in Figure 6-2.
  • 12.
  • 13. • As we can see from the figure 6-1 and table 6-1, the decoding process essentially requires the logic AND operation. The table and figure show the BCD inputs required to produce the decimal outputs 0 through 9. • Recalling that all HI logic states are required to produce HI outputs, notice that the circuit shows inverters to provide HI inputs at the AND gates when BCD inputs A,B,C and D are L0 (A̅,B̅,C̅ and D̅).
  • 14. • Also notice that all lines of the circuit are identified showing the input state and code place value for each input bit. For example, if the BCD code for the number 6 were to be decoded the input from table 6-1 would be 0110 or D̅CBA̅. In figure 6-2 a L0 at the input to INVERTERS (D) and (A)(circles) will produce a HI at these outputs (no circles). The remaining 2 input bits required to produce a HI output from AND gate (6), namely C and B are HI and will activate the gate without inversion. Looking at the input lines to gate (6) will verify that a HI will exist on all inputs for the code 0110 or D̅CBA̅ with place values (8̅421̅).
  • 15. • All remaining gates of figure 6- 2 can be analyzed in the same manner. A HI at the outputs would provide the signal required to activate a numeric readout.
  • 16. ANALYZING TROUBLE SYMPTOMS OF DECODER CIRCUIT AND ITS SIGNAL • Decoder circuit operation can be checked by noting the inputs and outputs. An analysis of the inputs and outputs usually indicates location of the circuit fault. Then, logic probe circuit tracing can be employed to isolate the exact location of the fault. • For example, in the BCD decoder circuit of figure 6-3, a defective gate will affect only one decimal output, the gate might be open or shorted, in which case the output would remain permanently L0 or HI.
  • 17.
  • 18. • On the other hand, if one of the INVERTERS were defective, the decimal outputs would be incorrect for several inputs. If the C̅ inverter were in a permanently HI state, for example, then as the BCD inputs proceeded through a count from 000 to 111, we would get the outputs shown in table 6-3.
  • 19.
  • 20. POST-TEST I.IDENTIFICATION 1.A DECODER can be thought of in the opposite sense as an __________. 2.What is the general rule for decoder, if the number of the inputs is equal to a number N, the decoder will produce _________ outputs. 3.__________ is used to provide decimal information from a binary coded input.
  • 21. 4.In the figure 6-1 and table 6-1, the decoding process essentially requires what kind of logic operation? 5.If one of the INVERTERS were defective, what would happened to the decimal output of a decoder circuit? II. Rewrite the following Input Binary Code into Digital Logic State. 1.0100 2.1001 3.0011 4.1100 5.1010
  • 22. III. Give the Output Decimal Number of the following Digital Logic State. 1.DC̅BA 2.D̅CBA̅ 3.D̅C̅B̅A 4.DC̅BA̅ 5.DCB̅A IV. Give the Output Decoder of the following Inputs in the general rule 2N. 1.N=3 2.N=5 3.N=8 4.N=10 5.N=12
  • 23. KEY ANSWERS I. 1.ENCODER 2.2N 3.BCD TO DECIMAL DECODER 4.AND OPERATION 5.INCORRECT FOR SEVERAL INPUTS II. 1.D̅CB̅A̅ 2.DC̅B̅A 3.D̅C̅BA 4.DCB̅A̅ 5.DC̅BA̅
  • 24. KEY ANSWERS III. 1.11 2.6 3.1 4.10 5.13 IV. 1.23 = 8 2.25 =32 3.28 =256 4.210 =1024 5.212 =4096