This document outlines a computer engineering project that uses an SMPCache simulator to evaluate cache performance under different design alternatives. It describes using the simulator to test workloads from SPEC benchmarks with varying cache size, levels, and mapping. Metrics like miss rate are recorded and analyzed to understand the impact of design choices and identify opportunities for higher cache performance through factors like increased size and associativity. Future work involves further experimentation and studying interactions between factors.
4. Cache performance parameters
Cache size
Cache block size
Cache levels
Cache mapping
Replacement policy
Unified cache or splitted
Very big range of combinations, so we need to
parameter performance evaluation.
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Organization of memory SMP or DSM
Number of processors 1,2,4,8,16,32,64or 128
Snoopy Protocol MSI, MESI or DRAGON
Bus arbitration random, LFU or LRU
Directory protocol SGI or off
Word Width (bits( 8,16,32or 64
Words in a block 1,2,4,8,16,32,64,128,up to 1024
Memory Blocks 1,2,4,8,16,32,64,up to 4194304.
Cache Levels 1,2,3or 4
Unified or splitted unified or data and instructions
Cache Blocks 1,2,4,8,16,32,64,128,256,512,1024or 2048
Mapping Direct, set-associative or fully associative
Cache sets in case of set-associative mapping
Replacement policy Random, LRU, LFU or FIFO
Writing strategy Writeback
Architectural characteristics
supported by SMPCache
18. Implementation
In each simulation experiment
Determine Main memory cache configuration
Select the desired option from list menu
Run the simulation
Record the result
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