1. 1 / 22
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2. www.thalesgroup.com
Project coordinator: THALES
Funding budget: 3,670,000€
Starting date: 15/10/2011
FlexTiles
www.flextiles.eu
Duration: 36 months
Philippe MILLET, HiPEAC 2012
Research & Technology
HiPEAC '12

3. 3 / 22
low volume
Cognitive radio
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low power consumption
Embedded Real-Time Applications
Smart camera
UAV
Fault-tolerance
Time To Market
adaptable product line
Adapt to environment  dynamicity, flexibility & dependability
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Industrial issues
otherwise use of this document is strictly prohibited without Thales prior written approval. ©THALES 2011. Template trtp version 7.0.8

4. 4 / 22 Challenges
address increasing application increase software development
dynamicity productivity of manycore
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-using self-adaptive capabilities -reduce Time to Market
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-reuse of legacy software
-reuse of hardware IPs.
increase accessibility to increase energy efficiency
manycore technologies
-for embedded systems
-propose a European alternative on
the worldwide market of this -andHigh-Performance Computing
technology (HPC) systems.
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5. 5 / 22 Objectives of the project
1) develop a heterogeneous manycore based on available IPs
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definition of generic interfaces
2) improuve programming efficiency of heterogeneous
manycores
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3) self-adaptation
thanks to virtualisation layer
4) develop a dynamic reconfigurable technology
pre-emption and relocation capabilities.
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6. 6 / 22 Other Projects
Existing manycores provide static allocation and sheduling
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• TILE-Gx™ 8000 from Tilera (16 to 100 cores)
• MPPA® from Kalray (256 to 1024 cores)
• PicoArray from Picochip (248 cores)
otherwise use of this document is strictly prohibited without Thales prior written approval. ©THALES 2011. Template trtp version 7.0.8
• FlexTiles (1 to thousands of cores)
Projects:
reconfigurable inside
Programmability
FlexTiles
Tsar Mosart
ADAM
Apple-Core
Morpheus
Aether
ReconOS
FOSFOR
Hardware Flexibility / dynamicity
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7. 7 / 22 1) develop a heterogeneous manycore system on a chip
Standardized
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GPP i DMA GPP i DMA GPP i DMA
N N N tiles and
O O O
LMEM ACC LMEM ACC LMEM ACC
C C C interfaces
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TILE TILE TILE
GPP i DMA GPP i DMA
N N
LMEM O
ACC NOC LMEM O
ACC
heterogeneous
C C
TILE TILE
accelerators
GPP i DMA GPP i DMA GPP i DMA
N N N
O O O
LMEM ACC LMEM ACC LMEM ACC
C C C
TILE TILE TILE
Heterogenous Many-Core
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8. 8 / 22
NoC
data
control
I
N
Tile
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LMEM
DMU
Tile core : generic part
internal com
GPP
I
I
A
IP in A
specific part
eFPGA
on DSP
Tile accelerators :
function
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1) interfaces
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9. 9 / 22 2) programming efficiency of heterogeneous manycores
Application
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Parallelisation, partioning
toolchain Compilation Synthesis, P&R
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relocatable binary code relocatable bitstream
Operating Library API
Virtualisation ACTION
operating layer
library Kernel Resource
Monitorin & MONITORING DIAGNOSIS
O = F(L)
Allocation SYSTEM
Hardware Abstraction Layer API
heterogenous Hardware Abstraction Layer
multicore
Hardware Tile
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10. 10 / 22 3) self-adaptation: virtualization layer
ACTION
Mapping
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MONITORING DIAGNOSIS
O = F(L)
SYSTEM
I/O
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Accelerator/Virtual Code
GPP I DMA GPP I DMA GPP I DMA
N N N
O O O
LMEM C LMEM C DSP LMEM C
I/O REC
GPP I DMA GPP I DMA GPP I DMA
N N
O
N
O O
allocation / binding
LMEM C REC LMEM C LMEM C REC
DSP
GPP I DMA GPP I DMA GPP I DMA
N N N
O O O
LMEM C REC LMEM C LMEM C
DDR DSP
Noc
DDR
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11. 11 / 22
www.flextiles.eu
Tile
Tile
Tile
Tile
Tile
Tile
Tile
Homogeneous manycore
Tile
FlexTiles: a 3D stacked chip
Tile
The information contained in this document and any attachments are the property of THALES. You are hereby notified that any review, dissemination, distribution, copying or
4) develop a new dynamic reconfigurable technology
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12. 12 / 22
Homogeneous manycore
www.flextiles.eu
Tile
Tile
NoC
Tile
Tile
Tile
Tile
Tile
FlexTiles: a 3D stack chip
Tile
Tile
Two layers communicating through one or several NoCs
The information contained in this document and any attachments are the property of THALES. You are hereby notified that any review, dissemination, distribution, copying or
4) develop a new dynamic reconfigurable technology
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13. 13 / 22
NoC
Homogeneous manycore
www.flextiles.eu
Tile
Tile
Tile
Tile
Tile
Tile
Tile
FlexTiles: a 3D stack chip
Tile
Tile
3D stacked reconfigurable layer
The information contained in this document and any attachments are the property of THALES. You are hereby notified that any review, dissemination, distribution, copying or
4) develop a new dynamic reconfigurable technology
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14. 14 / 22
NoC
Homogeneous manycore
www.flextiles.eu
3D stacked reconfigurable layer
Tile
Tile
Tile
Tile
Tile
Tile
Tile
Map Accelerated functions
FlexTiles: a 3D stack chip
Tile
Tile
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4) develop a new dynamic reconfigurable technology
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15. 15 / 22
NoC
Homogeneous manycore
www.flextiles.eu
3D stacked reconfigurable layer
Tile
Tile
Tile
Duplicate
Tile
Tile
Tile
Tile
FlexTiles: a 3D stack chip
Tile
Tile
The information contained in this document and any attachments are the property of THALES. You are hereby notified that any review, dissemination, distribution, copying or
4) develop a new dynamic reconfigurable technology
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16. 16 / 22
NoC
Homogeneous manycore
www.flextiles.eu
3D stacked reconfigurable layer
Tile
Tile
Tile
Migrate
Tile
Tile
Tile
Tile
FlexTiles: a 3D stack chip
Tile
Tile
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4) develop a new dynamic reconfigurable technology
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17. 17 / 22 4) develop a new dynamic reconfigurable technology
thread1
thread3 thread1 thread2thread2 thread4
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API
I/O Acc1 Acc1 Acc3 Acc4 DDR ctrl
Tile Tile Tile Tile Tile Tile
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NoC
Dynamic allocation
Dynamic allocation
I/O
Acc1 thread1 thread2
Acc3
thread1 thread2 thread3 thread4
Acc1
Acc4 API
Tools for Tools for
parallelisation parallelisation
and mapping and mapping
Application
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18. 18 / 22
GPP
on chip
shMEM
icache
dcache
dLMEM GPP
NI
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DSP
iLMEM DSP
dLMEM DSP
NI
data
NOC
NOC
NOC
NOC
NOC
control
bitstream
instruction
test/debug
eFPGA
iLMEM eFPGA
dLMEM eFPGA
NI
+
NI
ctrl
DDR
chip
DDR
NoC QoS
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19. 19 / 22
low latency
highly scalable
packet switching
wormhole protocol
www.flextiles.eu
power efficient and dependable
between nodes: no global clock, no even local clock
GALS: asynchronous logic in nodes, local synchronous cores
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ANoC (CEA)
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20. 20 / 22
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Globally Synchronous with time slots
Contention free routing by construction
wormhole routing specified at design time
Guaranteed levels of services and performances
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AEtheral NoC (TUe)
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21. 21 / 22 Results
• versatile accelerated multicore architecture
• SystemC simulator and FPGA demonstrators
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• Physical design of embedded reconfigurable technology
• to be implemented on a 3D stacked layer
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• HW and SW interfaces to address heterogenous manycores
• create or use standards
• Virtualisation layer code, kernel
• self adaptive
• heterogeneous manycore Tool chain
• design both multicore and accelerated functions at the same time
• Network selection according to required QoS
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22. 22 / 22 8 partners in 5 countries Consortium and questions
Partners & Third Country Main scientific and
Party technical contributions
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THALES France Infrastructure and
applications
KIT Germany Virtualisation layer
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TUE Netherlands Kernel ; NoC
CSEM Switzerland DSP
CEA France NoC ; 3D stacking
UR1 France Reconfigurable technology
SUNDANCE United FPGA Demonstrator
Kingdom
ACE Netherlands Parallelisation and
compilation Tools
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