State Of FPGA: Current & Future - A Panel discussion @ 4th FPGA Camp
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The panelists discussed their views on the current state and future of FPGAs. Mark expressed concerns about soft error rates and power densities in high-end FPGAs. Gordon said the industry is healthy but the race to more logic cells has pushed single architectures. Daniel said the line between FPGAs and ASICs is blurring and more niche and application-specific solutions will emerge. Chris said higher-level design flows will be needed to meet complexity demands. Umar viewed FPGAs as programmable processing engines well-suited for product architecture risk.
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State Of FPGA: Current & Future - A Panel discussion @ 4th FPGA Camp
- 8. Panelists Positions on FPGAs, Current & Future © FPGACentral.com – World’s 1 st FPGA Portal
- 14. Questions & Answers © FPGACentral.com – World’s 1 st FPGA Portal
Notes de l'éditeur
- Presentation Title
- FPGAs are growing in complexity at an alarming rate and are now the primary drivers for new process technologies. Today’s FPGAs contain the equivalent logic capacity of a 5 million gate ASIC design plus 30Mb RAM and various IP such as Gigabit I/O, DSP blocks and microprocessors. With this complexity comes new problems for the designer in reaching timing goals quickly and accurately. The physical interconnect (routing) of the FPGA dominates the overall percentage of delay in the circuit. Tools and methodologies have started to appear to address this, but more is needed. Power in FPGAs is also an increasing problem. While big FPGAs are not likely to be the choice for battery-powered applications, the large amounts of FPGA logic along with the routing to support it consumes increasing amounts of power and produce heat. Area optimizations and better utilization of local routing resources improves power On-chip microprocessors and other IP introduces complexity and additional special requirements. A software development environment to support processor-based FPGAs is needed. Xilinx offers Embedded Design Kit (EDK) and Altera offers System Builder for processor-based FPGA design. For verification, Real-time stimulus needed to test functionality Networking, Video/Audio, Processors Classic debug methodologies are failing Iterations in the lab extremely time consuming Too complex to debug with probes & educated guesses False errors more common with gate level debug tools More equivalence checking Faster than simulation Guarantees logical equivalence