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Code No: RAR05322201
RA
III B.Tech II Semester Supplimentary Examinations, Aug/Sep 2008
MICROPROCESSORS AND MICROCONTROLLERS
(Instrumentation & Control Engineering)
Time: 3 hours Max Marks: 80
Answer any FIVE Questions
All Questions carry equal marks
1. (a) Compare 8 bit processors and 16 bit pro cessors from the architectural view.
(b) Explain Over ow condition with 8 bit signed data. Generate Over ow ag
using other ags of 8086? [6+10]
2. (a) Give the assembly language implementation of the following.
i. DO - WHILE
ii. FOR [4+4]
(b) What is a recursive procedure? Write a recursive procedure to calculate the
factorial of number N, where N is a two-digit Hex number? [8]
3. (a) Discuss the system bus cycle of 8086 with a neat diagram? What is the use
of wait cycles? Compare wait and idle cycles?
(b) Design an I/O port decoder that generate the following low-bank I/O strobes:
00FEH, 00C8H, 00DEH, 00EEH. [8+8]
4. (a) What is BSR mode operation? How it is useful in controlling the interrupt
initiated data transfer for mo de 1 and 2?
(b) Explain the transistor bu er circuit used to drive 7-segment LEDs? [8+8]
5. (a) Draw the command register and mode register format of 8237 and explain
each bit?
(b) Show how 8237’s are cascaded to provide more number of DRQ’s and explain
the operation?
(c) Explain how memory to memory transfer is performed with 8237? [5+6+5]
6. (a) Discuss the sequence of operations performed in the interrupt acknowledge
cycle?
(b) What is the di erence between RET and IRET? Discuss the result, if RET
instruction is placed at the end of the interrupt service routine?
(c) What is the vector address of type 50H interrupt? [6+6+4]
7. In an SDK-86 kit 64KB SRAM and 32KB EPROM is provided on system and
provision for expansion of another 64KB SRAM is given. The on system SRAM
address map is from 00000H to 0FFFFH and that of EPROM is from F8000H to
FFFFFH. The expansion slot address map is from 80000H to 8FFFFH. The size
of SRAM chip is 32KB. EPROM chip size is 16KB. Give the complete memory
interface and also the address map for individual chips? [16]
1 of 2
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Code No: RAR05322201
RA
8. Interface two 8255’s to 8051 with starting address of 0F000H? Show the hardware
design? Write the instruction sequence to initialize all ports of rst 8255 as output
ports in mo de 0 and in the second 8255 port A as input in mode 1 and other ports
as input in mode 0. [16]
2 of 2
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05322201 Microprocessors And Microcontrollers Set1
- 1. www.studentyogi.com www.studentyogi.com Code No: RAR05322201 RA III B.Tech II Semester Supplimentary Examinations, Aug/Sep 2008 MICROPROCESSORS AND MICROCONTROLLERS (Instrumentation & Control Engineering) Time: 3 hours Max Marks: 80 Answer any FIVE Questions All Questions carry equal marks 1. (a) Compare 8 bit processors and 16 bit pro cessors from the architectural view. (b) Explain Over ow condition with 8 bit signed data. Generate Over ow ag using other ags of 8086? [6+10] 2. (a) Give the assembly language implementation of the following. i. DO - WHILE ii. FOR [4+4] (b) What is a recursive procedure? Write a recursive procedure to calculate the factorial of number N, where N is a two-digit Hex number? [8] 3. (a) Discuss the system bus cycle of 8086 with a neat diagram? What is the use of wait cycles? Compare wait and idle cycles? (b) Design an I/O port decoder that generate the following low-bank I/O strobes: 00FEH, 00C8H, 00DEH, 00EEH. [8+8] 4. (a) What is BSR mode operation? How it is useful in controlling the interrupt initiated data transfer for mo de 1 and 2? (b) Explain the transistor bu er circuit used to drive 7-segment LEDs? [8+8] 5. (a) Draw the command register and mode register format of 8237 and explain each bit? (b) Show how 8237’s are cascaded to provide more number of DRQ’s and explain the operation? (c) Explain how memory to memory transfer is performed with 8237? [5+6+5] 6. (a) Discuss the sequence of operations performed in the interrupt acknowledge cycle? (b) What is the di erence between RET and IRET? Discuss the result, if RET instruction is placed at the end of the interrupt service routine? (c) What is the vector address of type 50H interrupt? [6+6+4] 7. In an SDK-86 kit 64KB SRAM and 32KB EPROM is provided on system and provision for expansion of another 64KB SRAM is given. The on system SRAM address map is from 00000H to 0FFFFH and that of EPROM is from F8000H to FFFFFH. The expansion slot address map is from 80000H to 8FFFFH. The size of SRAM chip is 32KB. EPROM chip size is 16KB. Give the complete memory interface and also the address map for individual chips? [16] 1 of 2 www.studentyogi.com www.studentyogi.com
- 2. www.studentyogi.com www.studentyogi.com Code No: RAR05322201 RA 8. Interface two 8255’s to 8051 with starting address of 0F000H? Show the hardware design? Write the instruction sequence to initialize all ports of rst 8255 as output ports in mo de 0 and in the second 8255 port A as input in mode 1 and other ports as input in mode 0. [16] 2 of 2 www.studentyogi.com www.studentyogi.com