The document contains multiple choice questions about VHDL. VHDL is a hardware description language used to model electronic systems. An entity in VHDL describes the ports of a logic function. Ports can be inputs, outputs, or inouts. Concurrency in VHDL allows statements to be processed in parallel. The keyword 'wait' is used with edge specifications. When using a VHDL component, the port definitions must match the entity definition of the calling code.

1. A VHDL entity describes
A) The operation of a logic function
B) The ports of a logic function
C) The sequence of program function
D) The sequence of program instructions
A ports in VHDL is
A) An input
B) An output
C) A window
D) An input or output
An identifier that is legal in VHDL is
A) Output_1_A
B) Output__B
C) 3Phase
D) Input Alpha
The concurrency features of VHDL allows two or more statements to be processed
A) In series
B) In sequential
C) In parallel
What VHDL keyword is used in conjunction with an edge specification to cause the program to
act on the edge of a clock pulse?
A) Clear
B) Pause
C) Wait

2. D) None of the above
The VHDL identifier mode that allows a port identifier to act as both an input and an output is?
A) Multi
B) Inout
C) Feedback
D) Slave
When using a VHDL component, the component port definitions must
A) Match the entity definition of the VHDL code being called
B) Match the entity definition of the VHDL code calling the entity
C) Contains user-defined identifier name of the user's choice for the name of the component
D) None of the above
In structural VHDL,
Solution
1. A VHDL entity describes
B) The ports of a logic function
2. A ports in VHDL is
D) An input or output
3. An identifier that is legal in VHDL is

3. B) Output__B
4. The concurrency features of VHDL allows two or more statements to be processed
C) In parallel
5. What VHDL keyword is used in conjunction with an edge specification to cause the program
to act on the edge of a clock pulse?
C) Wait
6. The VHDL identifier mode that allows a port identifier to act as both an input and an output
is?
B) Inout
7. When using a VHDL component, the component port definitions must
B) Match the entity definition of the VHDL code calling the entity
8. In structural VHDL,