It contain the delays used in the different modelling in verilog code.

1. DELAYS IN VERILOG
Delays in Verilog
Presented BY:
Jitu Mistry
At eiTRA centre

2. Why delays and timing so important ?
 They allow a degree of realism to be incorporated into
the modeling process.
 The time taken for changes to propagate through a
module may lead to race conditions in other modules.
 Some designs, such as high speed microprocessors, may
have very tight timing requirements that must be met.
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3. Types of Delays.
 Depending on the design approach,
 Gate-level Modeling
 Dataflow Modeling
 Behavioral Modeling
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4. Gate level modelling
 Propagation delay :
through the gate, and the time taken for the output to actually
change state, according to input.
 Gate level modelling delay described below as:-
 Rise
 Fall Min/Typ/Max values
 Turn-off
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5. The rise delay is associated with a gate output transition
to a 1 from another value(0,x,z).
Format: operation #( Rise_Val, fall_Val ) a1( out, i1, i2);
Ex: and #(1 , 0 ) a1(out ,i1,i2);
//Rise=1, Fall=0, Turn-Off=0
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Rise delay

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 buf #(2,0) (out,in);

7. Fall delay
The fall delay is associated with a gate output transition to
‘0’ from another state ‘1’
Format: operation #( Rise_Val, fall_Val ) a1( out, i1, i2);
Ex:-> and #(0 , 1 ) a1(out ,i1,i2);
// Rise=0 Fall=1 Turn-Off=0
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buf #(0,2) (out,in);
buf #(2,3) (out,in);

9. The turn-off delay is associated with a gate output transition to the high
impedance value(z) from another value(0,1,x).
If the value changes to x, the minimum of three delay is considered.
Rise Delay 0,x,z -> 1
Fall Delay 1,x,z -> 0
Turn-Off Delay 0,1,x -> z
Number Of Delays Specified delays
1 Rise, fall and turn-off times of
equal length
2 Rise and fall times
3 Rise, fall and turn off
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Turn-off delay

10.  For each type of delay, there are three values, min,typ
and max can be specified.
 Any one value can be chosen at the start of the simulation
Because of IC fabrication process variations.
Ex:
And #( 2:3:4, 3:4:5, 4:5:6) a ( out, i1, i2 );
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Min, typ or max values

11.  In Verilog delays can be introduced with
#'num'
as in the examples below, where # is a special character
to introduce delay, and 'num' is the number of ticks
simulator should delay current statement execution.
 #1 a = b // Delay by 1, i.e. execute after 1 tick unit
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#'num'

12.  We can provide num value of different way by variable
or/and parameter
 Parameter delata= 10;
#delta out = in1& in2
Note: # There is no way we could synthesize delays, but
of course we can add delay to particular signals by
adding buffers.
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#'num'

13. #5 y = x + z; // line will execute after 5 unit delay
And
Y = #5 x + z; // assignment to y after the 5 unit delay
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#'num'

14. Dataflow Modelling
 As dataflow modelling use the concept of signals or values
 The delays are associated with the Net (e.g. a Wire)
along which the value is transmitted
 Delays values control the time between the change in a
right hand side operand and when the new value is
assigned to the left hand side.
#5 a = b; means a    b
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15. Dataflow Modelling
 Since values can be assigned to a net in a number of ways,
there are corresponding methods of specifying the
appropriate delays.
1. Regular Assignment Delay
2. Net Declaration Delay
3. Implicit Continuous Assignment
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16. Regular Assignment Delay
 To assign a delay in continuous assignment the delay
value is specified after the keyword assign.
 This is used to introduce a delay onto a net that has
already been declared.
 e.g. wire out;
assign #10 out = in1 & in2;
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Any change in values of in1 or in2
will result in the 10 time unit before
Recomputaion
Inertial delay

17. Net Declaration Delay
 The Delay to be attributed to a Net can be associated
when the Net is declared.
 e.g.
// net delays
wire #10 out;
assign out = in1 & in2;
// the same effect as the following, generally
preferable
wire out;
assign #10 out = in1 & in2;
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18. assign #10 out = in1 & in2;

19. assign #10 out = in1 & in2;

20. Implicit Continuous Assignment
 Since a net can be implicitly assigned a value at its
declaration, it is possible to introduce a delay then, before that
assignment takes place.
 E.g.
wire #10 out = in1 & in2;
// same as
wire out;
assign #10 out = in1 & in2;
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21. Inertial delay
 Inertial delay is a measure of the elapsed time during
which a signal must persist at an input of a device in order
for a change to appear at an output.
 A pulse of duration less than the inertial delay does not
contain enough energy to cause the device to switch.
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22. Transport delay
 It is like ideal conductors; that is, they may be modeled as
having no resistance.
 In that case the waveform at the output is delayed but
otherwise matches the waveform at the input.
 Transport delay can also be useful when modeling
behavioral elements where the delay from input to output
is of interest, but there is no visibility into the behavior of
delays internal to the device
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23. DELAYS IN BEHAVIOURAL MODELLING
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There are following method
 Delay-based timing control
Regular
Intra- assignment
Zero delay

24. REGULAR DELAY CONTROL
 Regular delay control is used when a non –zero
delay is specified to the left of a procedural
assignment
 This is sometimes also referred to as inter-
assignment delay control
 Example:#10 q = x+y;
 It simply waits for the appropriate number of
timesteps before executing the command.
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25. INTRA ASSIGNMENT DELAY
 Instead of specifying delay control to the left of tha
assignment, it is possible to assign a delay to the
right of the assignment operator.
 Example: q = #10 x+y;
 With this kind of delay ,the value of x+y is stored
at the time that the assignment is executed, but this
value is not assigned to q until after the delay
period.
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28. ZERO DELAY
 Zero delay is a method to ensure that a statement
is executed last,after all other statements in that
simulation time are execcuted.
 This is to to elminate race arround conditions.
 However if there are multiple zero delay
statements,the order between them is
nondeterministic.
 EX:#0 x=1
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29. SEQENTIAL BLOCKS
 The keywords begin and end are used to group
statements into seqential blocks.
 A statement is executed only after its preceeding
statement completes execution.
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31. PARALLEL BLOCKS
 Parallel blocks, specified by keywords fork and
join,provide intresting simulation features.
 Statements in a parallel block are executed
concurrently.
 Ordering of statements is controlled by delay or
event control assigned to each statement.
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33. Setup and Holdtime
 Very important in sequential logic.
 $setup(data_line, clk_line, limit);
 $hold(clk_line, data_line, limit);
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34. Thank you
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