1. K J Somaiya College of Engineering
Vidyavihar, Mumbai 400 077
Department: Electronics Engineering
Name of the Laboratory: VLSI
Year: Final year Semester: VII
Branch: Electronics
Subject: VLSI Design
List of Experiments
1. Spice simulation of NMOS inverter with a)Resistive load
b) Enhancement load
c) Depletion load
d) PMOS load
2. CMOS inverter layout and simulation using Magic and Spice3
3. NAND/NOR layout and simulation using Magic and Spice3
4. Boolean Expression layout and simulation using Microwind
5. Transmission gate layout and simulation using Microwind
6. Verilog programming and simulation :a) 4:1 mux b) 3:8 Decoder
7. Verilog programming and simulation : T- flip flop, counter (structural)
8. Verilog programming and simulation : State machines a) Moore b) Mealy

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Basic constructs and commands of Verilog
Verilog Constructs:
Basic Gates(and, or, xor):
These implement the basic logic gates. They have one output and one or more inputs.
In the gate instantiation syntax shown below, GATE stands for one of the keywords
and, nand, or, nor, xor, xnor.
Syntax:
GATE(drive strength)#(delays)instance_name1(output, input_1,input_2, …, input_N),
instance_name2(output,in1,in2,…,inN);
Wire:
A wire represents a physical wire in a circuit and is used to connect gates or modules.
The value of a wire can be read, but not assigned to, in a function or block A wire does
not store its value but must be driven by a continuous assignment statement or by
connecting it to the output of a gate or module. Other specific types of wires include:
1. wand(wired and);: The value of a wand depends on logical AND of all the drivers
connected to it.
2. wor(wired-or);: The value of a wor depends on logical OR of all the drivers
connected to it.
3. tri(three-state);: All drivers connected to a tri must be z, except one (which
determines the value of the tri).
Syntax:
wire[msb:lsb]wire_variable_list;
wand[msb:lsb]wand_variable_list;
wor[msb:lsb]wor_variable_list;
tri[msb:lsb]tri_variable_list;
Reg:
A reg(register) is a data object that holds its value from one procedural assignment to
the next. They are used only in functions and procedural blocks. A reg is a Verilog
variable type and does not necessarily imply a physical register. In multi-bit registers,
data is stored as unsigned numbers and no sign extension is done for what the user
might have thought were two’s complement numbers.

3. KJSCE/BE/ETRX/VII-SEM/2011-12
EXPERIMENT NO:
Title: 4:1 Multiplexer , 3:8 Decoder
Aim: To understand the conditional constructs and commands of
Verilog
Theory: Continuous assignment statement assign
A continuous assignment statement is the most basic statement in
dataflow modeling, used to drive a value onto net. This
assignment replaces gates in the description of the circuit and
describes the circuit at a higher level of abstraction. Continuous
assignment is done with an explicit assign statement or by
assigning a value to a wire during its declaration. Note that
continuous assignment statements are concurrent and are
continuously executed during simulation. The order of assign
statements does not matter. Any change in any of the right-hand
side inputs will immediately change a left-hand side output.
The syntax of the assign statement is as follows:
continuous_assign
::=assign[drive_strength][delay]net_assignment
list_of_net_assignment ::= net_assignment {net_assignment}
net_assignment ::= net_value = expression
Always Block
The always block is the primary construct in RTL modeling. Like
the continuous assignment, it is a concurrent statement that is
continuously executed during simulation. This also means that all
always blocks in a module execute simultaneously.
This is very unlike conventional programming languages, in which
all statements execute sequentially. The always block can be
used to imply latches, flip-flops or combinational logic. If the
statements in the always block are enclosed within begin … end,
the statements are executed sequentially. If enclosed within the
fork … join, they are executed concurrently (simulation only).
Syntax 1
always@(event_1 or event_2 or…)
begin
… statements …
end
Syntax 2
always@(event_1 or event_2 or …)
begin: name_for_block
… statements …

4. end
Conditional Operator: “?”
Conditional operator is like those in C/C++. They evaluate one of
the two expressions based on condition. It will synthesize to a
multiplexer.
Syntax
(cond)?(result if cond true):(result if cond false)
Case
The case statement allows a multi-path branch based on
comparing the expression with a list of case choices. Statements
in the default block executes when none of the case choice
comparisons are true (similar to the else blockin the if … else if
…else). If no comparisons, including default, are true,
synthesizers will generate unwanted latches. Good practice says
to make a habit of putting in a default whether you need it or not.
If the defaults are don’t cares, define them as ‘x’ and the logic
minimize will treat them as don’t cares. Case choices may be a
simple constant or expression, or a comma-separated list of
same.
case(expression)
case_choice1:
begin
… statements …
end
default:
begin
… statements …
end
endcase
if … else if … else
The if … else if … else statements execute a statement or block
of statements depending on the result of the expression following
the if. If the conditional expressions in all the if’s evaluate to false,
then the statements in the else block, if present, are executed.
There can be as many else if statements as required, but only
one if block and one else block. If there is one statement in a
block, then the begin … end statements may be omitted. Both
the else if and else statements are optional. However if all the
possibilities are not specifically covered, synthesis will generate
extra latches.
Syntax
if (expression)
KJSCE/BE/ETRX/VII-SEM/2010-11
begin
… statements …
end
else if (expression)
begin
… statements …
end
The multiplexer is a special combinational circuit that is one of the
most widely used standard circuit in digital design. The multiplexer
is a logic circuit that gates out several inputs to a single output.

5. The input is controlled by a set of select inputs. The figure shows
a block diagram of a 4:1 multiplexer. The truth table is shown
below.
Select Inputs Output
S1 S2 Y
0 0 I0
0 1 I1
1 0 I2
1 1 I3
Y = S1’ S0’ I0 + S1’ S0 I1 + S1 S0’ I2 + S1 S0 I3
Block
Diagram:
4:1 Multiplexer
KJSCE/BE/ETRX/VII-SEM/2010-11
A decoder performs the reverse function of the multiplexer. It has
one input and several outputs. The truth table of 3:8 decoder is
shown below.
Input Control Output
S0 S1 S2
0 0 0 11111110
0 0 1 11111101
0 1 0 11111011
0 1 1 11110111
1 0 0 11101111
1 0 1 11011111
1 1 0 10111111
1 1 1 01111111
Block
Diagram:
3: 8 Decoder
Roll No:
Signature of faculty in-charge
Conclusion:

6. KJSCE/BE/ETRX/VII-SEM/2011-12
EXPERIMENT NO:
Title:
T- flip flop, counter (structural)
Aim:
To understand behavioral and structural architecture
description in verilog
Theory: Need for behavioral description
Need for structural description

7. KJSCE/BE/ETRX/VII-SEM/2011-12
Logic and diagram for T- flip-flop
Logic and diagram for counter using T- flip-flops
Roll No:
Signature of faculty in-charge
Conclusion:

8. KJSCE/BE/ETRX/VII-SEM/2011-12
EXPERIMENT NO:
Title:
State machines a) Moore b) Mealy
Aim:
To describe sequential circuits in verilog and compare
performances of moore and mealy machines in terms of
area
Theory: 1) Design of sequence detector : Mealy type
KJSCE/BE/ETRX/VII-SEM/2010-11
2) Design of sequence detector : Moore type
Machine Area Delay
1)
Comparison :
2)
Roll No:
Signature of faculty in-charge
Conclusion:

9. KJSCE/BE/ETRX/VII-SEM/2011-12
EXPERIMENT NO:
Title:
Study of NMOS inverters
Aim:
To describe NMOS inverters in spice and compare their
performances in terms of VOH,VOL values and slope of
the transfer curve
Theory: 1) Resistive load inverter
2) Enhancement load inverter
KJSCE/BE/ETRX/VII-SEM/2010-11
3)Depletion load inverter
4) PMOS load( CMOS) inverter
Comparison :
VOH VOL
Comment on
transfer curve
Resistive load
Enhancement
load
Depletion load
CMOS
Roll No:
Signature of faculty in-charge
Conclusion:

10. KJSCE/BE/ETRX/VII-SEM/2011-12
EXPERIMENT NO:
Title:
Inverter layout using magic and simulation using spice
Aim:
To create an inverter layout using magic and simulate
using spice.
Theory: The inverter circuit is a circuit which inverts the input and
gives it as output. The inverter made over here is a CMOS
inverter. The CMOS inverter contains the PMOS transistor
in the pull up section and NMOS transistor in the pull
down section. The input is given to the gates of the two
transistors. and the output is taken at the junction of drain
of PMOS and drain of NMOS.
What is Magic?
Magic is an interactive system for creating and
modifying VLSI circuit layouts. With Magic you use a color
graphics display and a mouse or graphics tablet to design
basic cells and to combine them heirarchy into large
structures. Magic is different from other layout editors you
may have used. The most important difference is that
magic is more than just a color painting tool: it
understands quite a bit about the nature of the circuits and
uses this information to provide you with additional
operations. For example, magic has built in knowledge of
layout rules; as you are editing, it continuously checks for
rule violations. Magic also knows about connectivity and
transistors and contains a built in heirarchial circuit
extractors. Magic also has a plow operation that you can
use to stretch or compact cells. Lastly Magic has routing
tools that you can use to make the global interconnections
in the circuits.
Magic is based on the Mead-Conway style of design.
This means that it uses simplified design rules and circuit
structures. The simplifies make it easier for you to design
circuits and permit magic to provide powerful assistance
that would not be possible otherwise. However they result
in slightly less dense circuits that you could get using
more complex rules and structures. For example, magic
permits on manhattan designs (those whose edges are
vertical and horizontal). Circuit designers tell us that
conservative design rules cost 5 - 10 in density. We think
that the density sacrifice is compensated for by reduced
design time.
‘paint’ :- The ‘paint’ command is used to paint a selected
box in the layout window. This is followed by the name of

11. KJSCE/BE/ETRX/VII-SEM/2011-12
the region that is to be painted. This can be used to paint
any layer or contact or a via.
The syntax is as follows :
: paint layer
‘stretch’:-This command is used to increase or decrease
the size of selected layer. This command is followed by
‘up’ or ‘down’. And the size by which the layer is to be
changed.
‘save’ :- This command is used to save the current layout
magic file.
‘label’ :- This command is used to label a particular layer
in the layout. For this, left and right mouse button is
clicked in the same place and then command is typed;
followed by the label wanted.
Example- :label VDD
‘delete’ :- this command will delete the selected cell in the
layout.
:save filename – saves the file
:extract all – extracts electrical parameters from the layout
to enable simulation
Spice
Linux prompt> ext2spice -f spice3 filename
This command creates filename.spice file with the netlist
of active devices and node capacitances with sizes and
parameters corresponding to the Magic layout.
Additional cir file is created to give inputs to the nodes.
Input voltage is specified as a 0-to-5V pulsating voltage
(with 0-to-5V transition delayed by 1ns, rise time of 0.1ns,
fall time of 0.1ns, pulse width of 2ns, and period of 4ns)
Roll No:
Signature of faculty in-charge
Conclusion:
The inverter layout was created using MAGIC. It is an
interactive system used for modifying and creating VLSI
circuit layouts. It continuously checks for rule violations
as the user is editing. The various commands used argrid,
paint, label, save, stretch, etc.
The CMOS inverter was extracted and simulated using
SPICE3. To get proper VTC the (W/L)pmos_ 2.5(W/L)nmos
If you do not maintain the above proportion then the
proper VTC is not obtained.

12. KJSCE/BE/ETRX/VII-SEM/2011-12
EXPERIMENT NO:
Title:
NAND/NOR layout and simulation using Magic and
Spice3
Aim:
To extract and simulate NAND/NOR layout and
simulation using Magic and Spice3
Theory: NAND/NOR gate using CMOS
Stick diagrams
Roll No:
Signature of faculty in-charge
Conclusion:

13. KJSCE/BE/ETRX/VII-SEM/2011-12
EXPERIMENT NO:
Title:
Boolean Expression layout and simulation using
Microwind
Aim:
To simulate Boolean Expression layout using
Microwind
Theory: Boolean expression using CMOS
Stick diagram
Roll No:
Signature of faculty in-charge
Conclusion:

14. KJSCE/BE/ETRX/VII-SEM/2011-12
EXPERIMENT NO:
Title:
Transmission gate layout and simulation using
Microwind
Aim:
To simulate transmission gate layout and simulation
using Microwind
Theory: While both N-type and P-type transistors indeed have a
very large resistance between source and drain when
switched off, a detailed analysis reveals that the
resistance between source and drain depends on the
source and drain voltages when switched on. Especially,
there is a voltage drop across a conducting N-type
transistor when the source voltage is near VCC, and a
voltage drop across a conducting P-type transistor when
its source voltage is near GND. (Note that this poses no
problem in the static CMOS gates, where all source
contacts of N-type transistors are connected to GND and
all source contacts of P-type transistors are connected to
VCC.)
Therefore, the use of single N-type or P-type transistors as
switches is limited to circuits where the voltage drop
across the conducting transistors is not critical. A series
connection of transistors used as switches is usually not
possible in digital circuits.
But a combination of N-type and P-type transistors allows
to realize efficient switches in CMOS technology. The
circuit consists of one N-type and one P-type transistor
connected in parallel and controlled by inverted gate
voltages. This circuit, called a transmission gate (T-gate)
A T-gate requires that the N-type and P-type transistors
have inverted gate voltages.
If the gate voltage of the N-type transistor is 'GND', the Ptype
transistor has a gate voltage of 'VCC' and both
transistors are non-conducting. On the other hand, if the
gate voltage of the N-type transistor is 'VCC' and the gate
voltage of the P-type transistor is 'GND', both transistors
are conducting. If the source voltage is near VCC, there is
a voltage drop across the N-type transistor but (almost) no
voltage drop across the P-type transistor. If the source
voltage is near GND, the N-type transistor has (almost) no
voltage drop. Because of the symmetry of standard MOS

15. transistors, there is no reason to differentiate between
source and drain in a T-gate.
KJSCE/BE/ETRX/VII-SEM/2011-12
Stick diagram of transmission gate
Roll No:
Signature of faculty in-charge
Conclusion: