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Introduction to Programmable Networks
Intel@MYNOG
Clarence Anslem (Intel Network Communications APJ - Solution Architect)

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Agenda
§ Why do we need a Programmable Networks?
§ Is it possible to build a Programable Switch?
§ How can you create packet processing algorithms?
§ Use Cases
§ Next Steps & References
§ Q&A

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Traditional Network Devices
OS
Network
Function
Driver
Fixed Function Chip (ASIC)
Data
Flow
Data
Flow

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Why do we need a programmable network?
§ The World of Computing § The World Of Networking
1) Buy a computing device
• An embedded board
• A computer
• A VM in the cloud
2) Write a program in a high-level
language
3) Profit! J
1) Beg the OEM
2) Beg the ASIC Vendor
3) Wait 1 – 2 Years
4) Change Direction / Focus :(
Building the next killer product:

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How is this possible?
From a fixed algorithm to a programmable solution!

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Bottom Up vs Top Down Approach
OS
Network
Function
Driver
Fixed Function Chip
OS
Network
Function
Driver
Programmable Chip (P4 Target)
P4
Program
P4
Compiler

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P4 Introduction
§ Programming
§ Protocol-independent
§ Packet
§ Processors
P4 goals:
§ Protocol independence
- Define a packet parser
- Define a set of type match+action tables
§ Target Independence
- Program without the knowledge of packet processing device, let
compiler configure target details
§ Reconfigurability
- Allow users to change parsing and processing in the field
ü May 2013: Initial Idea & Name P4
ü Sept 2014: The first P4(14) spec
ü May 2017: The first P4 (16) spec (Architecture Model)

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What type of hardware can be programmed
“P4 Targets” & Common Development Tools
IntelTofino 3 – 25.6 Tbps
Broadcom Tomahawk 4 25.6 Tbps (Fixed Function)
Platform
Multiport Switches
IPU & Smart NICS Host (P4 DPDK)
FPGA Platform
P4 SDE P4 Compiler Front-end
P4 Visualization
C Model
Hardware
SDK
Tofino Back-end
C Model
Hardware
SDK
IPU Back-end
DPDK
Pipeline
SDK
DPDK Back-end
table routing {
key = { ipv4.dstAddr : lpm; }
actions = { drop; route; }
size : 2048; }
control ingress() {
apply {
routing.apply(); }
}
P4 Program
Hardware
SDK
FPGA Back-end
Network
Apps
Network
Apps
TDI

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Inside a Programmable Switch
Parser
Control
§ Programmer declares the headers that should be recognized & their order
In the incoming packet
§ The header types, and their structures & parser behaviour defined in the
P4 program
§ Programmer defines the tables and the exact processing algorithm
§ These block allow processing on the packet within the pipeline
§ Match-action table chain execution
§ Checksum verification and recalc
§ Deparsing
Protocol Independent Switching Architecture (PISA)

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Inside a Programmable Switch
• Packet is parsed into individual headers (parsed
representation)
• Headers and intermediate results can be used for
matching and actions
• Headers can be modified, added or removed
• Packet is deparsed (serialized)
• Feed-forward architecture
• Constant processing latency
• Stage-local resources
• Multiple simultaneous lookups are possible
• One packet per clock
• Many packets are processed in parallel
Protocol Independent Switching Architecture (PISA) in Action
Packet

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How does it all work together?
Parser
Match + Action
Tables
Packet Metadata
Queues /
Scheduling

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How does it all work together?
1
Protocol
Authoring
L2_L3.p4
2
Compile
3
Load
Eth VLAN
IIPv4 IPv6
Parser
Match + Action
Tables
Packet Metadata
Queues /
Scheduling
4
Control
Run-time API
Driver
Switch / NIC OS
5 Run

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How does it all work together?
1
Protocol
Authoring
VXLAN.p4
2
Compile
3
Load
Eth VLAN
IIPv4 IPv6
Parser
Match + Action
Tables
Packet Metadata
Queues /
Scheduling
4
Control
Run-time API
Driver
Switch / NIC OS
5 Run
UDP VXLAN

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P4 Application
P4 Application can be Hardware based or Software Based

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Use Case : In band Network Telemetry (INT)
INT Source
Instruments packets for
Telemetry
Intel® Deep Insight Network Analytics
Software
Log, Analyze, Replay and Visualize
INT Sink
Removes
metadata
Data-plane
Telemetry
In-band network
telemetry (INT.P4)
Intelligent
deduplication
and triggers
Line rate monitoring
Hardware primitives
Add INT Header: Hop ID, ingress timestamp,
egress timestamp, queue occupancy, matched
rules
INT Transit
Adds metadata based on
INT instructions Original
Packet sent
to end host
Source
Host
1 How did it get here? Why is it here? How long was it delayed?
Answer for every packet... 2 3 Why was it delayed?
4
INT metadata sent
to Deep Insight for
monitoring
Cluster
Mode
Destination
Host
+ +
Packet

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Use Case: 5G User Plane
Move the UPF function into the SRV6 Data Plane
§ 5G architecture enables lower latencies with distributed UPF architecture.
§ SRv6 MUP takes this one step further by transforming the mobile user plane from session to
routing based. (Think Internet).
§ Doing so eliminates needs for additional UPF functions in the data plane.

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Use Case: 5G User Plane
3 Entities in this SRv6 MUP Architecture:
§ MUP-GW translates GTP <> SRv6 and Vice Versa
§ MUP Controller transforms received Mobile Session information from 5G core to Routing information,
then advertises them to MUP PE’s & GW through BGP
§ MUP PE performs routing of packets based on IP route received from MUP Controllers
MUP-GW
MUP-PE
MUP-PE

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Summary
§ What we discussed?
§ Programmable Packet Processors enable innovation in networking
§ Programmable hardware is a reality today
• Intel Programmable Data Plane Pipeline & various targets including Tofino™ ASICS
• P416 language
§ Next Steps
§ Join Intel Connectivity Research Program (ICRP) https://intel.com/icrp
§ Attend Intel Connectivity Academy (ICA) http://intel.com/ica
§ Check out Softbank SRv6 MUP Solution
ü https://www.softbank.jp/en/sbnews/entry/20220329_01
ü https://networkbuilders.intel.com/social-hub/webcast/srv6-mobile-user-plane-breaking- barriers-between-mobile-network-and-internet
§ P4 Website https://p4.org/
§ Start to Innovate!!!

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