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A low power wide range horizontal Phase-Locked Loop (PLL) design, for generating precise pixel clock, from a noisy and low frequency horizontal synchronization signal (HSYNC) is presented in this paper. It is mainly applicable in analog interface of digital video display systems as pixel clock generator. In the proposed PLL, a fast phase tracking scheme with low jitter is implemented using digital blocks. A time-to-digital converter (TDC) and a digital delta-sigma modulator (DSM) are used to perform the fast phase tracking and a Digital Filter is used to eliminate reference clock jitter.