3. ®
MARKET CONVERGENCE
IS DRIVING DESIGN CONVERGENCE
MARKET CONVERGENCE DESIGN CONVERGENCE
Communications
Hardware Software
Computing
Multimedia
Digital Analog
IC Board
Consumer
3 CADENCE DESIGN SYSTEMS, INC.
4. ®
High Speed Design Challenges IC Board
1
• System timing
Clock 4
Driver
Setup
Hold
2 Tco
D0
3
Flight Time
D0
– What is the maximum data rate for reliable data transfer?
• Waveform integrity
D1 D1
D2 D2
Driving Receiving
D0 D1 D2
– Do signals meet applicable electrical requirements?
• Crosstalk
– Do the signals interfere with each other?
• Power and/or ground plane stability
– Are power voltages at the ICs sufficiently controlled?
• EMI (differential and common mode)
– Are critical signals radiating too much energy?
– Are power planes producing common-mode radiation?
4 CADENCE DESIGN SYSTEMS, INC.
5. ®
PCB System Design Flow and Products
Communications Functional
Functional NC Sim
Verification
Verification PSpice/AWB
Computing
SPECCTRAQuest C
Multimedia
Exploration
PCB Design Infrastructure
O
C Design Entry S Capture CIS N
O I Concept HDL S
N T
Floorplanning R
S A A
SPECCTRAQuest
T N I
Consumer R A N
A High-Speed L Allegro T
I PCB Layout Y SPECCTRA
M
IC Board N S A
Digital Analog T I SPECCTRAQuest N
S S A
IC G
E
Packaging Advanced Package R
Designer
5 CADENCE DESIGN SYSTEMS, INC.
6. ®
IC Board
PCB System Design Flow and Products
Communications Functional
Functional NC Sim
Verification
Verification PSpice/AWB
Computing
SPECCTRAQuest C
Multimedia
Exploration
PCB Design Infrastructure
O
C Design Entry S Capture CIS N
O I Concept HDL S
N T
Floorplanning R
S A A
SPECCTRAQuest
T N I
Consumer R A N
A High-Speed L Allegro T
I PCB Layout Y SPECCTRA
M
IC Board N S A
Digital Analog T I SPECCTRAQuest N
S S A
IC G
E
Packaging Advanced Package R
Designer
6 CADENCE DESIGN SYSTEMS, INC.
7. ®
SPECCTRAQuest products today
PCB Systems IC-Packaging
Model Management Environment
Power Integrity (PI) SPECCTRAQuest
Power Integrity
SPECCTRAQuest SPECCTRAQuest
SI Expert IC Packaging (SQIC)
Signal Integrity (SI)
SPECCTRAQuest
Signal Explorer
An environment for
creation, verification and management
of all types of models
7 CADENCE DESIGN SYSTEMS, INC.
8. ®
IC Board
Introducing the Design Flow
• High speed design issues must be managed throughout the PCB
design process
Model Pre-Route Post Route
Simulation Development Sol’n-Space Analysis
& Verification Analysis Verification
Topology Constraint
Layout Entry & Driven
Floorplanning Layout
8 CADENCE DESIGN SYSTEMS, INC.
9. ®
IC Board
SPECCTRAQuest in the PCB Design flow
Physical Layout
Physical Layout
Exploration
Exploration Design/Implementation
Design/Implementation FP
FP
Place
Place Route
Route
Simulation
Simulation Verification
Verification
Design Specs
SQ-SigXP
SQ-SigXP Concept HDL Expert
Concept HDL Expert SQ
SQ Allegro Expert
Allegro Expert
CM
CM CM
CM CM
CM CM
CM
I/O
models SPECCTRAQuest
SPECCTRAQuest
CM
CM
• Model Verification SPECCTRA
• Topology explorations
• Rules development • Timing driven floorplanning
• Post placement verification
9 • Post route verification
CADENCE DESIGN SYSTEMS, INC.
10. ®
Constraint Driven Layout
• Design rule violations during
interactive routing are identified
in real-time
• Autorouter follows design rules -
powerful integration with
SPECCTRA!
• Because solution space analysis
has defined a set of conditions
under which the nets are known
to work, chance of first-pass
success is high.
– Nets can be ripped up and
rerouted, as long as they still
adhere to the design rules
10 CADENCE DESIGN SYSTEMS, INC.
11. ®
PSD 14.0 Constraint Manager
• Common, powerful environment for constraint entry / editing / management
and verification
• Single mechanism for managing constraints throughout the design process
11 CADENCE DESIGN SYSTEMS, INC.
12. ®
Constraint Manager – Key Features
• Spreadsheet-based graphical
interface
– No cryptic formats or
cumbersome updating
• Provides unsurpassed Integration
across the entire design flow
– Consistent Front to Back solution
– No translations with static
constraint data
– Directly integrated with
schematic and PCB databases
– Analysis engines can update
spreadsheet data interactively
12 CADENCE DESIGN SYSTEMS, INC.
13. ®
SPECCTRAQuest Power Integrity
• Innovative technology developed and proven by Sun
Microsystems, now commercialized by Cadence Design
Systems, Inc. to address Power Delivery issues in high-speed
PCB System Designs.
• A design tool / methodology used to design and optimize the
frequency-dependent characteristics of Power Delivery
Systems in high-speed system designs
• An integrated solution to allow many quick iterations of
“change-simulate-analyze”
• Introduced in PSD 14.1 release
CADENCE DESIGN SYSTEMS, INC.
14. ®
Power Delivery Requirements Trend
Year Voltage Power Current Frequency Ztarget
(Volts) (Watts) (Amps) (MHz) (m-Ohms)
1990 5 5 1 16 250
1993 3.3 10 3 66 54
1996 2.5 30 12 200 10
1999 1.8 90 50 600 1.8
2002 1.2 180 150 1200 0.4
• Power dissipation and longer battery life fueling decreasing chip
power supply voltages
– Maximum allowable supply ripple decreases accordingly
• SoC, SiP fueling trend towards devices with large number of
devices
– The instantaneous switching current required is enormous
• The maximum acceptable power supply ripple voltage determines
the target impedance which must be maintained across the PCB
CADENCE DESIGN SYSTEMS, INC.
15. ®
Power Delivery System Design Challenges
• Power supply droop
– Alters system timing and can cause Setup failures
– Can cause sampling errors that results in a system crash
• Unreliable power delivery system design can cause increased
common-mode EMI preventing product shipment due to
compliance problems
• Power delivery system impedance is frequency-dependent
– Must be controlled for all frequency range of all transient currents
Increases Development Costs and
Increases Development Costs and
Time to Market is LOST!
Time to Market is LOST!
15 CADENCE DESIGN SYSTEMS, INC.
16. ®
Power Delivery System Design -
How it is done today
• Standalone analysis tools
– Design data translation is left up to the user
– Changes to the design resulting from simulation is manual
• Use Time Domain simulation
– Power delivery system impedance is frequency-dependent!
– With only time domain simulation, it is like searching for needle in a
haystack
• Over design - add more de-coupling capacitors than necessary
– Expensive solution that may not work
16 CADENCE DESIGN SYSTEMS, INC.
17. ®
The Cadence approach
• Allow users to determine the needs of the power delivery system
– Target impedance
– Decoupling capacitor requirements
• Provide frequency domain analysis to find problem areas
• Provide an integrated PCB design editor to optimize capacitor
placement
Develop reliable power delivery system
Develop reliable power delivery system
while shortening design cycle time
while shortening design cycle time
17 CADENCE DESIGN SYSTEMS, INC.
18. Introducing … ®
SPECCTRAQuest Model Integrity
(in v14.2)
PCB Systems IC-Packaging
Power Integrity (PI) SPECCTRAQuest
Power Integrity
SPECCTRAQuest SPECCTRAQuest
SI Expert IC Packaging (SQIC)
Signal Integrity (SI)
SPECCTRAQuest
Signal Explorer
Model Integrity (MI) SPECCTRAQuest
(in v14.2) Model Integrity for
An environment
creation, verification and management
of all types of models
18 CADENCE DESIGN SYSTEMS, INC.
19. ®
SQ Model Integrity
• Family of products that offers model creation, manipulation and
verification environment
– First release (PSD release 14.2) will offer the basic creation/editing and
sanity check environment for IO buffer models for following formats
– Cadence (DML)
– Quad [translator only]
– IBIS 3.2 [.ibs, .pkg, .ebd files]
– Future releases will offer advanced options that will provide verification
environment and handle different kinds of models
– Capacitor models for use with SPECCTRAQuest Power Integrity
– S-Parameters
– IC Package models
– Connector/FPGA models
– Link with PCB Librarian Expert series
19 CADENCE DESIGN SYSTEMS, INC.
21. ®
Demonstration Overview
• Model development and validation using SPECCTRAQuest Model
Integrity
• Constraint Development using SPECCTRAQuest SigXP
• Topology development using SPECCTRAQuest Floorplanner
• Constraints verification throughout the process
• System level verification using Design Link capability
• Power Integrity
21 CADENCE DESIGN SYSTEMS, INC.
22.
23. ®
Brief Description - SPECCTRAQuest 14.2
• SQ/Allegro, SQIC/APD UI Synchronization
Allow users to switch between SQ & Allegro and SQIC & APD plus
following commands to be changed in SQ
– Display > Element to replace Info > Item
– Logic > Net Schedule to replace Topology > Edit Pin Order
– Place > Manually to replace Floorplan > Component Place
23 CADENCE DESIGN SYSTEMS, INC.
24. ®
Brief Description –
SPECCTRAQuest SI Expert 14.2
• Custom measurements
Custom measurements and Custom Stimulus will be available when
simulating from the board level through the CM. In prior releases they
were only available from SigXP
• Differential Signalling improvements
Extraction and simulation of coupled differential pairs in SQ, SigXP
24 CADENCE DESIGN SYSTEMS, INC.
25. ®
Brief Description - Constraint Manager 14.2
• Concept Database Synchronization
Synchronizes constraints stored as Schematic properties and
CM worksheets
• Custom Measurement
Provides SigXP’s custom measurement capability in CM.
Ability to store custom measurements and to display
measurement results in CM [requires SQ SI Expert]
• Cross Probing Improvements
Cross probing with Allegro to handle segments/ratsnest, pin
pairs, DRCs and Clines
25 CADENCE DESIGN SYSTEMS, INC.
Editor's Notes
Spreadsheet style allow you to sort, manipulate your design netlist to easy managing both electrical and physical constraints
SPECCTRAQuest Power Integrity module is a new add on option to SPECCTRAQuest SI Expert. It embeds proven technology from Sun Microsystems, Inc along with design and analysis environment from Cadence to address power delivery issues in high-speed PCB systems design. SPECCTRAQuest Power Integrity embodies a methodology used to design and optimize frequency dependent characteristics of power delivery systems in high speed systems design. It offers an integrated design and analysis environment to allow users many quick iterations of “change-simulate-analyze” in a short period of time.
Over the past decade, power delivery requirements for modern high-speed systems have been increasing rapidly even as the supply voltages have been dropping from 5V in early 1990s to less than 2V in systems being designed today. Chart above shows how the current requirements have grown 5 times faster than the voltages have dropped on most high-speed systems with microprocessors and complex bus architectures. This has resulted in complex high-speed microprocessor based designs requiring over 100 watts of power to be delivered to it. As the supply voltage has dropped in these systems, the tolerance ripple voltage has shrunk as well. 5% allowed ripple in a 5V system meant that the supply voltage could tolerate a swing of 0.25V. The same 5% ripple in a 1.8V system means the swing cannot be more than 0.09V! The systems are becoming more sensitive as the supply voltage drops. The need to reduce the supply voltage will continue to be driven by the battery life and thermal concerns. Most high-speed systems that have front end or post layout SI/Crosstalk simulations performed assume a clean dependable supply voltage. The approach was to sprinke more capacitors than needed to avoid hot spots. Any that were missed were caught in a prototype debug stage. This approach drives up the system per unit cost and complexity (harder to place and route when real-esate is tight).
Power Delivery System design errors show up in various places. Unreliable power delivery (supply droop) can cause timing failures, which can result in system crashes. Improperly addressed hot spots in a high-speed system can increase common mode EMI preventing the product from shipping. Not solving the problem or addressing it too late in the cycle increases development costs and causes the product to miss its time to market window of opportunity, which can be fatal for many products in a competitive market place.
How do people deal with these issues today? Most people tend to deal with it either by over-designing (a bypass cap per power supply pin per device) or by adding an iteration after the prototype debug shows problems. Both approaches are becoming unacceptable if the system cost or real-estate is an issue. Certainly adding an iteration to build a prototype eats into the precious time to market window for most companies building complex high-speed PCB systems. Some companies that use simulation for power delivery system design use standalone time domain (TD) simulation engines to find the voltage swing. The problem is that the cause of the swing is not identified by the TD simulation. Leaving the user to guess at the cause, make a fix and then run simulation again to see if the problem is solved or not. This is the “shooting in the dark” approach. There is no gurantee of convergence. There is a better approach……….
The approach that Cadence has taken is a better approach. It investigates the problem in the frequency domain to identify the cause and also to suggest a solution that can fix the problem. The approach is rooted in the fact that power delivery system’s impedance is freuency dependent and must be controlled for all frequency ranges from DC to daylight. In addition to simulating in frequency domain to identify the problem and suggest a solution, SPECCTRAQuest Power Integrity offers an environment that makes multiple iterations of “change-simulate-analyze” very quick and easy. It offers an intergated design and analysis environment allowing the users to focus on the problem instead of struggling with data translation issues between the CAD system and the analysis engines.