MIXED SIGNAL VLSI TECHNOLOGY BASED SoC DESIGN FOR TEMPERATURE COMPENSATED pH MEASUREMENT
1.
2. MIXED SIGNAL VLSI TECHNOLOGY BASED SoC
DESIGN FOR TEMPERATURE COMPENSATED
pH MEASUREMENT
S. K. Tilekar1, A. S. Powar1 and B. P. Ladgaonkar1
1- VLSI Design & Research Centre
Post Graduate Department of Electronics
Shankarrao Mohite Mahavidyalaya, Akluj, Dist. Solapur (MS)
t_shivaprasad@rediffmail.com, bladgaonkar@yahoo.com
3. Abstract
An innovative field of embedded system exhibit wide
spectrum of applications particularly in the field of
instrumentation [1]. The VLSI devices like FPGA and CPLD
provide the reconfigurability for digital design only. Therefore,
for analog parts, the designers have to rely on off chip
hardware. This exhibits constraints in instrumentation [2]. The
emergence of the innovative technology called mixed signal
based VLSI design provides unique solution to above problem
[3]. Cypress semiconductor is performing pioneering job in the
field of mixed signal based programmable system on chip and
vendoring the PSoC5 device with remarkable features [4].
Deploying the features of PSoC5, a system on chip is designed
for temperature compensated pH measurement of the solution.
Keyword: Mixed Signal PSoC5, ADC, Programmable Gain
Amplifier, pH measurement.
6. Soft as well as hard IP Cores
FPGA platform
Core of the computing device
Specific IDE for system development
SoB to SoC
7. Static as well as Dynamic configurability IP Cores
FPGA platform
Advanced microcontroller Core (ARM Core)
Specific IDE for system development
P rogrammable
S ystem
o n
C hip
8. – Hardware programmability
Programmable analog blocks
Programmable digital blocks
Programmable interconnect
Programmable I/Os
Programmable clocks
Selectable power supply
– Integration as an SoC
9. 32-bit ARM Cortex-M3 CPU core
DC to 80 MHz operation
Flash program memory, up to 256 KB, 100,000 write cycles, 20-year retention, and
multiple security features
Up to 64 KB SRAM memory
2-KB electrically erasable programmable read-only memory (EEPROM) memory, 1
million cycles, and 20 years retention
Low voltage, ultra low power
Wide operating voltage range: 0.5 V to 5.5 V
Low power modes including: 2-μA sleep mode
Versatile I/O system
28 to 72 I/Os (62 GPIOs, 8 SIOs, 2 USBIOs)
LCD direct drive from any GPIO, up to 46×16 segments
All GPIOs configurable as open drain high/low, pull-up/pull-down, High-Z, or strong output
Configurable GPIO pin state at power-on reset (POR)
Digital peripherals
20 to 24 programmable logic device (PLD) based universal digital blocks (UDBs)
Full-Speed (FS) USB 2.0 12 Mbps using internal oscillator
Four 16-bit configurable timers, counters, and PWM blocks
Library of standard peripherals
Library of advanced peripherals
10. Analog peripherals
1.024 V ±0.1% internal voltage reference across –40°C to +85°C (14 ppm/°C)
Configurable delta-sigma ADC with 8- to 20-bit resolution
Two SAR ADCs, each 12-bit at 1 Msps[2]
80-MHz, 24-bit fixed point digital filter block (DFB) to implement finite impulse
response (FIR) and infinite impulse response (IIR) filters
Four 8-bit 8 Msps current IDACs or 1-Msps voltage VDACs
Four comparators with 95-ns response time
Four uncommitted opamps with 25-mA drive capability
Four configurable multifunction analog blocks. Example configurations are
programmable gain amplifier (PGA), transimpedance amplifier (TIA), mixer, and
Sample and Hold
Programming, debug, and trace
Precision, programmable clocking
11.
12.
13. Voltage output ranges: 1.020-V and 4.080-V full scale
Software- or clock-driven output strobe
Data source can be CPU, DMA, or Digital components
14. Gain steps from 1 to 50
High input impedance
Selectable input reference
Adjustable power settings
15. Single or differential connections
Adjustable between 2 and 32 connections
Software controlled
Connections may be pins or internal sources
No simultaneous connections
Bidirectional (passive)
16. Selectable resolutions, 8 to 20 bits (device dependent)
Eleven input ranges for each resolution
Sample rate 10 sps to 384 ksps
Operational modes:
Single sample
Multi-sample
Continuous mode
Multi-sample (Turbo)
High input impedance input buffer
Selectable input buffer gain (1, 2, 4, 8) or input buffer
bypass
Multiple internal or external reference options
Automatic power configuration
Up to four run-time ADC configurations
17.
18. Implements the industry-standard Hitachi HD44780 LCD display Driver
chip protocol
Requires only seven I/O pins on one I/O port
Contains built-in character editor to create user-defined
Custom characters
Supports horizontal and vertical bar graphs
19. Linear current output: 1 μA/K
Wide temperature range: −55°C to +150°C
2-terminal device: voltage in/current out
Laser trimmed to ±0.5°C calibration accuracy (AD590M)
Excellent linearity: ±0.3°C over full range (AD590M)
Wide power supply range: 4 V to 30 V
Sensor isolation from case
Low cost
20. 1) The visual method
2) The photometric method
3) The potentiometric method
21. E = Eo – K Tk pH
Nernst Factor
K = 0.19841 (273.15+T oC)
22. Execute boot program:
--initialise general purpose resources;
--configure application specific modules;
--initialise run time environment;
--disable interrupt;
call main application routine;
Void main()
{
Start system timers;
Initialise application specific modules;
Initialise global variables;
Initialise application specific channels;
Enable interrupts;
While(1)
{
Wait for events(Enabled interrupts);
Read values from input channels;
Execute control procedure & compute
actuation data;
output actuation data to output
channels;
}
}
B) Application programme routine
A) Boot programme algorithm
STRUCTURE OF FIRMWARE
23. #include <device.h>
#include <stdio.h>
float pH_Input_Signal();
float Temp_Input_Signal();
void soft_delay(unsigned int count);
int i=1,j=1;
float result=0,pH_Result,Average_pH,pH_value,pH_Temp_Copensated,pH_valueDirect;
float Temp_Result,Temp_value,Average_Temp,Temp_Calibrated;
30. Temp Measured in o
C
(Thermometer)
Temp dependent
NERNST volt in mV
From system (PSoC)
Temp dependent
NERNST volt in mV
From datasheet
20 58.18 58.16
25 59.17 59.16
30 60.16 60.15
35 61.13 61.14
40 62.13 62.13
45 63.14 63.12
50 64.13 64.12
55 65.12 65.11
60 66.12 66.10
65 67.11 67.09
70 68.09 68.08
75 69.10 69.08
80 70.09 70.07
31. The system is calibrated to pH scale and
implemented for measurement of temperature compensated
pH of the solution. The pH value shown by the system under
investigation are identical to that of measured by standard
pH meter. Thus SoC designed to measure pH of the solution
is more reliable and accurate.
32. 1) Y. Sukanya, S. Pathapati, “FSK Modem Using PSoC”, International journal of
soft computing and engineering, 2 3 (2012) 451.
2) L.M. Franca-Neto , P. Pardy, M.P. Ly, R. Rangel, S. Suthar, T. Syed, B. Bloechel,
S. Lee, C. Burnett, D. Cho, D. Kau, A. Fazio and K. Soumyanath, “Enabling
High-Performance Mixed-Signal System-on-a-Chip (SoC) in High Performance
Logic CMOS Technology”, Symposium on VLSI Circuits Digest of Technical
Papers, (2002)164-167.
3) L.S.Y. Wong, S. Hossain, A. Ta, J. Edvinsson, D.H. RivasandH. Naas, “A very
low-power CMOS mixedsignal IC for implantable pacemaker applications” IEEE
Journal of Solid-State Circuits, 39 12 (2004) 2446-2456.
4) M. Nagata, J. Nagai, T.Morie and A. Iwata, “Measurements and Analyses
ofSubstrate Noise Waveform in Mixed-Signal ICEnvironment,” IEEE
Transactions on CAD, 19 6 (200) 671-678.
5) K. Makie-Fukuda, T. Kikuchi, T. Matsuura, M. Hotta, “Measurement of digital
noise in mixed-signal integrated circuits”, IEEE Journal of Solid-State Circuits,
30 2 (1995) 87-92.
33. Research Activities
MRP : 01 Completed
Publications
: International Journals 01
: International Journals (Communicated) 01
: National Journals 01
: National Journals (Communicated) 01
: Proceedings International 02
: Proceedings National 42
Papers presented in conferences
: International 01
: International (Abroad) 01
: National 12