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VHDL Entity

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Ramasubbu .P
Ramasubbu .P

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VHDL ENTITY VHDL 1. ver.8a
In this chapter ,[object Object],[object Object],[object Object],[object Object],VHDL 1. ver.8a
What is an entity? Overall structure of a VHDL file VHDL 1. ver.8a Entity Library declaration Entity declaration Architecture body
What are they? VHDL 1. ver.8a Entity declaration Architecture body A VHDL file Library declaration, e.g. IEEE library Defines Input/Output pins The processing Entity
An example a comparator in VHDL VHDL 1. ver.8a The comparator chip: eqcomp4 a3 a2 a1 a0 equals b3 b2 b1 b0 equals VHDL for programmable logic , Skahill, Addison Wesley A=[a3,a2,a1,a0] B=[b3,b2,b1,b0]
An example of a comparator ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],VHDL 1. ver.8a Entity declaration: define IOs Architecuture body: functional definition
How to read it ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],VHDL 1. ver.8a Port defines the I/O pins. Entity enclosed by the entity name – eqcomp4 (entered by the user) ,[object Object],[object Object],[object Object],[object Object]
Entity declaration Define Input/Output (IO) pins VHDL 1. ver.8a Entity Library declaration Entity declaration Architecture body
Entity declaration: define the IO pins of the chip ,[object Object],[object Object],[object Object],[object Object],VHDL 1. ver.8a The comparator chip: eqcomp4 a3 a2 a1 a0 equals b3 b2 b1 b0 Two input buses (a3,a2,a1,a0) (b3,b2,b1,b0) and one output ‘equals’
Work example 1.1 ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],VHDL 1. ver.8a
More on Entity Declaration ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],VHDL 1. ver.8a **User defined variables are in Italic.
IN, OUT, INOUT, BUFFER ,[object Object],[object Object],[object Object],[object Object],VHDL 1. ver.8a
Worksheet 1.2 Example/Exercise: IN, OUT, INOUT, BUFFER ,[object Object],[object Object],VHDL 1. ver.8a From VHDL for programmable logic , Skahill, Addison Wesley
The architecture body Define the internal architecture/operation VHDL 1. ver.8a Entity Library declaration Entity declaration Architecture body
Architecture body: define the operation of the chip ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],VHDL 1. ver.8a Architecuture body
How to read it ,[object Object],[object Object],[object Object],[object Object],VHDL 1. ver.8a 6 architecture dataflow1 of eqcomp4 is 7 begin 8 equals <= ' 1 ' when ( a = b ) else ' 0 ’; 9-- “comment” equals is active high 10 end dataflow1 ;
Worksheet 1.3: Write the entity of this device ,[object Object],VHDL 1. ver.8a Worksheet VHDL1.3
Worksheet 1.4: Draw the schematic circuit ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],VHDL 1. ver.8a Worksheet VHDL1.4
Summary ,[object Object],VHDL 1. ver.8a

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VHDL Entity

  • 1. VHDL ENTITY VHDL 1. ver.8a
  • 2.
  • 3. What is an entity? Overall structure of a VHDL file VHDL 1. ver.8a Entity Library declaration Entity declaration Architecture body
  • 4. What are they? VHDL 1. ver.8a Entity declaration Architecture body A VHDL file Library declaration, e.g. IEEE library Defines Input/Output pins The processing Entity
  • 5. An example a comparator in VHDL VHDL 1. ver.8a The comparator chip: eqcomp4 a3 a2 a1 a0 equals b3 b2 b1 b0 equals VHDL for programmable logic , Skahill, Addison Wesley A=[a3,a2,a1,a0] B=[b3,b2,b1,b0]
  • 6.
  • 7.
  • 8. Entity declaration Define Input/Output (IO) pins VHDL 1. ver.8a Entity Library declaration Entity declaration Architecture body
  • 9.
  • 10.
  • 11.
  • 12.
  • 13.
  • 14. The architecture body Define the internal architecture/operation VHDL 1. ver.8a Entity Library declaration Entity declaration Architecture body
  • 15.
  • 16.
  • 17.
  • 18.
  • 19.