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Design and development of MIL-STD-1553 based engineering model
1. “Master Course in Space Transportation Systems”
Candidate: Ing. Raul Cafini
Supervisor: Prof. Ing. Marcello Onofri
Vitrociset S.p.A. Tutor: Ing. Giulio Troso
Ing. Ciaccini Massimo
3. The six-months post-lectures stage activity was
conducted c/o Vitrociset S.p.A. (VCS) :
◦ Via Tiburtina 1020, Rome – Italy;
◦ Tutor (Thanks to): Ing. Giulio Troso, Ing. Massimo Ciaccini;
Objective: design and development an Engineering
Model (EM) for Electrical Ground Support Equipment
(EGSE/SCOE) in support of European Space Agency
environments.
◦ The approach has to be compliant to ECSS and other
standards;
◦ The activity has to be carried out on a both theoretical and
practical way;
Ing. Raul Cafini - Master STS @
Vitrociset S.p.A. 3
4. A spacecraft and its payload must
be able to withstand the extreme
stress of launch phase and space
environment.
To help during the assembly, integration, testing and validation
campaigns manufactors build different Ground Support
Equipment:
o Mechanical-GSE (MGSE), Electrical-GSE (EGSE), …
Electrical Ground Support Equipment (EGSE):
o Telecommand (TC) sending / Telemetry (TM) acquisition;
o Data processing, archiving and retrieval;
o Human ⇆ Machine Interaction (HMI);
o …
Ing. Raul Cafini - Master STS @
Vitrociset S.p.A. 4
5. Satellite
(UUT)
Testing is very extensive, calls for automated test equipment
that helps to shorten test durations ⇒ SCOE
SCOEs are usually provided for each subsystem of a satellite:
◦ Remote control from a Central Check-Out System (CCS)
◦ Standalone mode via a local user interface (HMI).
The purpose is to test device units (Units Under Test) to
check-out all systems before and after the integration and
until launch;
◦ Data-Bus management (MIL-STD-1553, SpaceWire, … )
◦ Radio Frequency (RF) and Telemetry and Telecommand (TTC)
transmitting and receiving equipment;
SCOE
◦ Power Supply & Monitoring;
◦ …
EGSE
Ing. Raul Cafini - Master STS @
Vitrociset S.p.A. 5
6. On Board
Computer
BC
Primary Bus (A)
Military specification for Digital Time
Secondary Bus (B)
Division Data Bus & Protocol definition: RT … RT BM
◦ Command/Response, Multiplexed;
Radar,
◦ Dual-redundant (Bus A/B), Bidirectional; GNC
Sensors
HK
◦ 1Mbps serial, high bit error reliability (1/106);
Developed due the growing complexity of integrated
avionics systems:
◦ First utilization (1978) in the F-16 Falcon and AH-64A Apache;
Three different type of bus element:
◦ Bus Controller (BC): master device, decide which RT can
communicate on the bus;
◦ Remote Terminal (RT): slave devices such as sensors,
instruments, …
◦ Bus Monitor (BM): slave device, receiving bus traffic and extracting selected
information (i.e. HouseKeeping data);
Used as communication standard on many programs:
◦ Submarines, Tanks [...] Satellites/and Space Systems including
VEGA Launcher, Sentinel-3, and International Space Station (ISS)
Ing. Raul Cafini - Master STS @
Vitrociset S.p.A. 6
7. Vettore Europeo di Generazione Avanzata
Italy leading project (> 60%)
Single-body launcher with three solid rocket
stages (P80 + Z23 + Z9) and one liquid
upper stage (AVUM)
Designed to launch small payloads:
o Reference mission 1,500 kg @ 700 km
in polar orbit.
First launch, from CSG@Kourou early 2012.
MIL-STD-1553 is used as avionic bus for
allow communication between stages and
the On Board Computer (OBC)
o VCS works on Vega Control Bench;
Ing. Raul Cafini - Master STS @
Vitrociset S.p.A. 7
8. Future ESA space mission, third satellite in
the GMES program;
Medium-resolution optical/radar
altimetry earth/sea observation;
Launch date around 2013;
Mission characteristics:
o Launch mass: ~1250 kg
o Launcher: Vega / Soyuz from Kourou
o Orbit: Sun-synchronous @ 800 km
Applications
o Sea and land colour data, surface
temperature and topography data
MIL-STD-1553 used as main data/control bus
between satellite instruments and payloads;
o VCS works on satellite SCOEs;
Ing. Raul Cafini - Master STS @
Vitrociset S.p.A. 8
9. Define and Develop a Software Architecture:
Modeled into layers:
◦ Data Link, Transfer and Application layers;
Customizable for Checkout (SCOE) & Timeline definition;
o Common Core + Project-Dependant parts;
Validate the Engineering Model on a standard-based
platform:
◦ i.e. MIL-STD-1553;
Following base guidelines from VCS under-development
participating ESA projects:
◦ VEGA Launcher;
◦ Sentinel-3 (S3) Satellite;
Ing. Raul Cafini - Master STS @
Vitrociset S.p.A. 9
10. Cross-Platform:
◦ Multiple Operative Systems: GNU/Linux (main development) and Windows
(partial implemented);
Reusable:
◦ Common (general) + Customizable (project-dependant) code;
Modular:
◦ Common SCOE Core elements (Logger(s), Data Archiver(s), … )
◦ Multiple Standard-Dependent Frameworks
MIL-STD-1553, SpW, Can-BUS, …
Performant:
◦ Possible use in High Rate / Heavy Load data traffic applications;
Documented:
◦ Auto-Generated documentation from source code (HTML);
Ing. Raul Cafini - Master STS @
Vitrociset S.p.A. 10
11. Hardware platform based on:
◦ HP Workstation xw6200, Intel Xeon µP (Dual Processor),
2GB RAM;
◦ Aim API-1553 PCI Card;
Software:
◦ GNU/Linux O.S. (OpenSUSE 10.3):
Performance (customizable O.S. setup to achieve better
response and processing performance)
Real-Time capability;
◦ Integrated Development Environment (Eclipse):
Multi-Language support (C/C++, Java, XML, … )
Plug-in Extension (JDT, CDT, Window
Builder, XMLEditor, … )
Ing. Raul Cafini - Master STS @
Vitrociset S.p.A. 11
12. HLCS
Command/HK TC/TM
LLCS
EGSE Engineering 1553HMI
PISQ Repository SCOE Core
IPC 1553 HMI
Util Main Window
(Queue, Socket
(Thread)
SHM)
FSM Packetizer Logger Archiver
MIL-STD-1553
1553 HMI
LLCS Framework
OS/HW Driver’s API for Java Virtual Machine
MIL-STD-1553 Board (Aim) (JRE)
GNU/Linux OS
LAN / MIL-STD-1553 Bus
Ing. Raul Cafini - Master STS @
Vitrociset S.p.A. 12
13. This component provide: EGSE Engineering
Finite State Machine (FSM):
◦ Allow the creation of a custom FSM to define a
series of logical states for application SCOE Core
Logger:
◦ Log history of user commands and system
FSM Packetizer Logger Archiver
responses for traceability and debbuging;
Creation of .log text files;
Archiver: MIL-STD-1553
Framework
◦ Data traffic archiving on binary file to collect and
capture any kind of data for future analisys;
Creation of .bin binary data files;
Packetizer*: LogFile
(.log)
Archive
(.bin)
◦ Packet/Unpacket data from/to different
Protocol Standards (CCSDS, PUS, etc.)
* (future extended capabilities)
Ing. Raul Cafini - Master STS @
Vitrociset S.p.A. 13
14. This component provide: EGSE Engineering
Simulate concurrent bus devices:
◦ BC, RT (up to 31) & BM;
SCOE Core
Load Bus / Frame Setup
◦ From XSD validated XML file;
Frame composition in terms of FSM Packetizer Logger Archiver
Major/Minor Frames, Transfers, ...
◦ To/From, Type, Data, … ; MIL-STD-1553
Framework
Error Injection / Detection;
IRIG-B Timecode:
◦ Inter-Range Instrumentation Group timecode,
◦ Internal / External reference; BusSetup
(XML)
FrameSetup
(XML)
Validate
BusSchema FrmSchema
(XSD) (XSD)
Ing. Raul Cafini - Master STS @
Vitrociset S.p.A. 14
15. Now a little demo of how
system works…
Ing. Raul Cafini - Master STS @
Vitrociset S.p.A. 15
21. Defined a modular and extendable
software architecture as defined
from requirements;
Implemented EGSECoreArchitecture+MIL-STD-1553
Framework (Server-side);
Implemented a simple Human-Machine Interface
(HMI) to interact with the system (Client-side)
Additional stage activities:
◦ Assist VEGA Control Bench group for test activity;
◦ Assist IMBTS Project;
Ing. Raul Cafini - Master STS @
Vitrociset S.p.A. 21
22. Continue development
from EM to Product
Industrialization;
o Extends current functionalities;
o Deep unit-test and debugging;
o Developing new Standard-Based Frameworks (i.e.
SpaceWire, CAN-Bus, … );
Use on a pilot project to evaluate the adapting
and maintenance efforts;
Ing. Raul Cafini - Master STS @
Vitrociset S.p.A. 22