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2Sem-MTech-Low Power VLSI Design Homework - Unit1

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Dr. Shivananda Koteshwar
Dr. Shivananda Koteshwar
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13       EVEN     SEMESTER                     LOW  POWER  VLSI  DESIGN-­‐2-­‐MTech-­‐     Homework  –  UNIT1             Shivananda  Koteshwar     Professor,  E&C  Department,  PESIT  SC           1) Introduction     5) Low  Power  Design  Circuit  Level   2) Device  and  Technology  Impact  on  Low   6) Low  Power  Architecture  and  Systems   Power   3) Power  Estimation,  Simulation  Power   7) Low  Power  Clock  Distribution   Analysis   4) Probabilistic  Power  Analysis   8) Algorithm  and  Architectural  Level   Methodologies   Reference  Books:   1. Kaushik  Roy,  Sharat  Prasad,  “  Low-­‐Power  CMOS  VLSI  Circuit  Design”  Wiley,  2000   2. Gary  K.  Yeap,  “  Practical  Low  Power  Digital  VLSI  Design”,  KAP,  2002   3. Rabaey,  Pedram,  “  Low  Power  Design  Methodologies”  Kluwer  Academic,  1997     UNIT  1:     Introduction:  Need  for  low  power  VLSI  chips,  Sources  of  power  dissipation  on  Digital   Integrated  circuits,  Emerging  Low  power  approaches,  Physics  of  power  dissipation  in  CMOS   devices.       P e o p l e s   E d u c a t i o n   S o c i e t y   S o u t h   C a m p u s   ( w w w . p e s . e d u )  
Low  Power  VLSI  Design  (2nd  Semester)                                                                                  UNIT  1  HW  v1.0     Paper Submission Team 1 Need for Low Power VLSI Chips Subramanya / Ravindra 2 Failure Mechanism with Temperature Shivukumar / Amaranath increase 3 Ultra Low Power Device and Applications Sagar / Akshay 4 VI Characteristics of Inverter and Passgate Santosh / Ajit 5 Low/High Vt Cells and MTCMOS Cells Nitin / Zowresh 6 Cooling strategies in a chip Swatishree / Chaitra 7 Packaging techniques and +/- of each Geetanjali / Harshitaa 8 Sources of Power Dissipation Rajshekhar / Vinayak 9 Scaling and different parameters Sandeep / Muralidhar Questions to be answered by all (All are 6marks questions unless specified otherwise) 1. What are the sources of power dissipation in digital ICs ? 2. With usual notation derive the equation for short circuit power dissipation in a CMOS inverter (10m) 3. Discuss the techniques to reduce power dissipation (10m) 4. Write an explanatory notes on physics of power dissipation in MOSFET devices? 5. Explain the need for Low Power VLSI Design 6. Discuss about the dynamic dissipation in CMOS 7. A 32 bit off chip bus operating at 5V and 66MHz clock rate is driving a capacitance of 25pF/bit. Each bit is estimated to have a toggling probability of 0.25 at each clock cycle. What is the power dissipation in operating the bus 8. Explain the basic principle of Low Power Design 9. Derive the most important equation for power dissipation in digital VLSI circuits taking into account the charging and discharging of capacitance in CMOS circuits 10. Explain the effects of input signal slope and output loading capacitance on short circuit current   Shivoo  Koteshwar’s  Notes                                          2                                                                                          shivoo@pes.edu        

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2Sem-MTech-Low Power VLSI Design Homework - Unit1

  • 1. 13       EVEN     SEMESTER                     LOW  POWER  VLSI  DESIGN-­‐2-­‐MTech-­‐     Homework  –  UNIT1             Shivananda  Koteshwar     Professor,  E&C  Department,  PESIT  SC           1) Introduction     5) Low  Power  Design  Circuit  Level   2) Device  and  Technology  Impact  on  Low   6) Low  Power  Architecture  and  Systems   Power   3) Power  Estimation,  Simulation  Power   7) Low  Power  Clock  Distribution   Analysis   4) Probabilistic  Power  Analysis   8) Algorithm  and  Architectural  Level   Methodologies   Reference  Books:   1. Kaushik  Roy,  Sharat  Prasad,  “  Low-­‐Power  CMOS  VLSI  Circuit  Design”  Wiley,  2000   2. Gary  K.  Yeap,  “  Practical  Low  Power  Digital  VLSI  Design”,  KAP,  2002   3. Rabaey,  Pedram,  “  Low  Power  Design  Methodologies”  Kluwer  Academic,  1997     UNIT  1:     Introduction:  Need  for  low  power  VLSI  chips,  Sources  of  power  dissipation  on  Digital   Integrated  circuits,  Emerging  Low  power  approaches,  Physics  of  power  dissipation  in  CMOS   devices.       P e o p l e s   E d u c a t i o n   S o c i e t y   S o u t h   C a m p u s   ( w w w . p e s . e d u )  
  • 2. Low  Power  VLSI  Design  (2nd  Semester)                                                                                  UNIT  1  HW  v1.0     Paper Submission Team 1 Need for Low Power VLSI Chips Subramanya / Ravindra 2 Failure Mechanism with Temperature Shivukumar / Amaranath increase 3 Ultra Low Power Device and Applications Sagar / Akshay 4 VI Characteristics of Inverter and Passgate Santosh / Ajit 5 Low/High Vt Cells and MTCMOS Cells Nitin / Zowresh 6 Cooling strategies in a chip Swatishree / Chaitra 7 Packaging techniques and +/- of each Geetanjali / Harshitaa 8 Sources of Power Dissipation Rajshekhar / Vinayak 9 Scaling and different parameters Sandeep / Muralidhar Questions to be answered by all (All are 6marks questions unless specified otherwise) 1. What are the sources of power dissipation in digital ICs ? 2. With usual notation derive the equation for short circuit power dissipation in a CMOS inverter (10m) 3. Discuss the techniques to reduce power dissipation (10m) 4. Write an explanatory notes on physics of power dissipation in MOSFET devices? 5. Explain the need for Low Power VLSI Design 6. Discuss about the dynamic dissipation in CMOS 7. A 32 bit off chip bus operating at 5V and 66MHz clock rate is driving a capacitance of 25pF/bit. Each bit is estimated to have a toggling probability of 0.25 at each clock cycle. What is the power dissipation in operating the bus 8. Explain the basic principle of Low Power Design 9. Derive the most important equation for power dissipation in digital VLSI circuits taking into account the charging and discharging of capacitance in CMOS circuits 10. Explain the effects of input signal slope and output loading capacitance on short circuit current   Shivoo  Koteshwar’s  Notes                                          2                                                                                          shivoo@pes.edu