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Writing more complex models (continued)

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Mohamed Samy

Modeling more complicated logic using sequential statements Skills gained: 1- Model simple sequential logic using loops 2- Control the process execution using wait statements This is part of VHDL 360 course

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VHDL 360© by: Mohamed Samy Samer El-Saadany
Copyrights Copyright © 2010 to authors. All rights reserved All content in this presentation, including charts, data, artwork and logos (from here on, "the Content"), is the property of Mohamed Samy and Samer El-Saadany or the corresponding owners, depending on the circumstances of publication, and is protected by national and international copyright laws. Authors are not personally liable for your usage of the Content that entailed casual or indirect destruction of anything or actions entailed to information profit loss or other losses. Users are granted to access, display, download and print portions of this presentation, solely for their own personal non-commercial use, provided that all proprietary notices are kept intact. Product names and trademarks mentioned in this presentation belong to their respective owners. VHDL 360 © 2
Objective Modeling more complicated logic using sequential statements Skills gained: Model simple sequential logic using loops Control the process execution using wait statements VHDL 360 © 3
Sequential Statements Sequential Statements Case statement If statement loop statements While Loop For Loop Wait statement Think Hardware VHDL 360 © 4
While-Loop <Loop_Label> While <condition> loop -- list of sequential statements end loop; 5 VHDL 360 © Syntax: ,[object Object],<Loop_Label> optional label to identify the loop <condition> Boolean expression that evaluates to either TRUE or FALSE Example 1: count number of ONES in vector A A: (7DOWNTO0), count: integerrange0to8; PROCESS(A)IS VARIABLEtempCount, iteration:integerrange0to8; BEGIN iteration :=0;tempCount:=0; my_loop:WHILE (iteration <= 7) LOOP if A(iteration)= '1' then tempCount:=tempCount+1; endif; iteration := iteration +1; ENDLOOP; Count <=tempCount; ENDPROCESS;
Skills Check 6 VHDL 360 © After the loop finishes what will be the value of “count” signal? While count <10loop count <= count +1; Endloop;
Skills Check (Soln.) ,[object Object]
To fix this :“count” must be a variable 7 VHDL 360 © While count <10loop count := count +1; Endloop; Or the process should be suspended inside the while loop using a wait statement While count <10loop count <= count +1; <wait statement>-- more on “Wait” later Endloop; Golden rules of thumb ,[object Object]
Signals are updated after the process suspends,[object Object]
For-Loop <Loop_Label> for <idenifier> in <range> loop -- list of sequential statements end loop; 9 VHDL 360 © Syntax: ,[object Object],<Loop_Label> optional label to identify the loop <identifier> loop iterator that can only be read inside the loop and is not available outside it <Range> loop range and can be one of the following <integer> to <integer> <integer> downto <integer> Example 2: Anding A with each bit in the vector B_bus SIGNAL A: std_logic; SIGNALB_bus,C_bus:std_logic_vector(7downto0); … process( A,B_bus) begin foriin7downto0loop C_bus(i)<= A andB_bus(i); endloop; Endprocess;
For-Loop 10 VHDL 360 © Example 3: 8-bit shift register Library ieee; Use ieee.std_logic_1164.all; entityshift_registeris Port(clk, D, enable :inSTD_LOGIC; Q :outSTD_LOGIC); endentity; architecture Behavioral ofshift_registeris signalreg:std_logic_vector(7downto0); begin process(clk) begin ifrising_edge(clk)then if enable = '1' then reg(7)<= d; foriin7downto1loop reg(i-1)<=reg(i); endloop; endif; endif; endprocess; Q <=reg(0); end Behavioral;
Exercise 1 The following diagram and flow chart show a “Serial In Parallel Out” register’s interface and describe how it behaves. 11 VHDL 360 ©
Exercise 1 To complete the “Serial In Parallel Out” we need to do the following: Add necessary assignments to the reset condition Add a for loop to shift each bit of the internal register “reg” to the right Decide the condition by which the 8 queued values goes outside the register 12 VHDL 360 © libraryieee; useieee.std_logic_1164.all; useieee.std_logic_unsigned.all; entityserialinparalleloutis port(clk:instd_logic; d :instd_logic; rst:instd_logic; enable :instd_logic; ready :outstd_logic; q :outstd_logic_vector(7downto0)); endserialinparallelout;
Exercise 1 architecture behave ofserialinparalleloutis signal count:std_logic_vector(2downto0); begin process(clk) variablereg:std_logic_vector(7downto0); begin ifrising_edge(clk)then ifrst= '1' then Q <= X"00";-- hexadecimal format <Here> else Ready <= '0'; if enable = '1' then < Add the loop Here> reg(7):= d; count <= count+1; … VHDL 360 © 13
Exercise 1 … if count = ?? then Q <=reg; count <="000"; Ready <= '1'; endif; endif; endif; endif; endprocess; end behave; VHDL 360 © 14
Sequential Statements Sequential Statements Case statement If statement loop statements While Loop For Loop Wait statement VHDL 360 © 15
Wait Statement wait [ sensitivity clause ] [ condition clause ] [timeout clause] ; 16 VHDL 360 © Syntax: Process’ sensitivity list is only one means for controlling when a process is executed. Process execution can also be controlled with one or more waitstatements The wait statement causes suspension of a process Sensitivity clause, condition clause and timeout clause can optionally coexist in the same wait statement sensitivity_clause: onsignal_name Condition clause: until condition timeout_clause: fortime_expression Example 4: wait; -- suspends process forever waiton clock;-- suspends process execution until an event occurs on clock waitfor10 ns;-- suspends process execution for 10 ns waituntil A < B andenable = '1';-- suspends process until the condition is true waituntil A = '0' for2 ns;-- after A equals 0 wait 2 ns then resume execution of process
Wait Statement Example 5: Counter generator 1 Architecture waveform oftestbenchis signal z :std_logic_vector(2downto0); Begin process-- no sensitivity list begin foriin0to7loop z <=conv_std_logic_vector(i,3);-- converts integer to std_logic_vector waitfor20 ns; endloop; wait; Endprocess; Endarchitecture; 17 VHDL 360 ©
Skills Check Architecture waveform oftestbenchis signal z :std_logic_vector(2downto0); Begin process begin foriin0to7loop z <=conv_std_logic_vector(i,3); waitfor20 ns; endloop; -- wait; Endprocess; Endarchitecture; 18 VHDL 360 © What will happen if we remove this “wait”?
Skills Check (Soln.) Architecture waveform oftestbenchis signal z :std_logic_vector(2downto0); Begin process begin foriin0to7loop z <=conv_std_logic_vector(i,3); waitfor20 ns; endloop; -- wait; Endprocess; Endarchitecture; 19 VHDL 360 © The waveform will not stop when Z reaches “111”, Z will start over again from “000”
Skills Check 20 VHDL 360 © Catch me If you can! ,[object Object]
After fixing the problems, draw the waveforms
When do you think one of them can’t be used for clock generation?,[object Object]
Architecture “behave2” can’t generate a clock with duty cycle other than 50%,[object Object]
Process 3 differs only at initialization time…afterwards the simulation results will be similar to Process 1 & Process 2,[object Object],[object Object]
Conversion Functions 25 VHDL 360 © Reference page Syntax: conv_integer() Converts a std_logic_vector type to an integer; Requires: library ieee; use ieee.std_logic_unsigned.all; Or use ieee.std_logic_signed.all; conv_integer(std_logic_vector); Example 6: libraryieee; useieee.std_logic_unsigned.all; signal tour:std_logic_vector(3downto0); signal n:integer; n <=conv_integer(tour);
Conversion Functions 26 VHDL 360 © Reference page conv_std_logic_vector() Converts an integer type to a std_logic_vector type Requires: library ieee; use ieee.std_logic_arith.ALL; Syntax: conv_std_logic_vector(integer, number_of_bits) Example 7: libraryieee; useieee.std_logic_arith.all; signal tour:std_logic_vector(3downto0); signal n:integer; tour <=conv_std_logic_vector(n,4);
Sharpen your Saw
Lab work Write the code for a Fibonacci sequence generator: Output is the sum of the two previous outputs (0,1,1,2,3,5,8,13,…) Port names & types must be: Clk, rst: std_logic Fib_out : integer Don’t use inoutports rst: synchronous reset 28 VHDL 360 ©
Knight Rider LEDs 29 ,[object Object],The shining led moves from left to right then from right to left…etc Port names & types must be: Clk, rst, enable: std_logic knight: std_logic_vector(7 downto 0) Don’t use inoutports rst: synchronous reset VHDL 360 ©

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Writing more complex models (continued)

  • 1. VHDL 360© by: Mohamed Samy Samer El-Saadany
  • 2. Copyrights Copyright © 2010 to authors. All rights reserved All content in this presentation, including charts, data, artwork and logos (from here on, "the Content"), is the property of Mohamed Samy and Samer El-Saadany or the corresponding owners, depending on the circumstances of publication, and is protected by national and international copyright laws. Authors are not personally liable for your usage of the Content that entailed casual or indirect destruction of anything or actions entailed to information profit loss or other losses. Users are granted to access, display, download and print portions of this presentation, solely for their own personal non-commercial use, provided that all proprietary notices are kept intact. Product names and trademarks mentioned in this presentation belong to their respective owners. VHDL 360 © 2
  • 3. Objective Modeling more complicated logic using sequential statements Skills gained: Model simple sequential logic using loops Control the process execution using wait statements VHDL 360 © 3
  • 4. Sequential Statements Sequential Statements Case statement If statement loop statements While Loop For Loop Wait statement Think Hardware VHDL 360 © 4
  • 5.
  • 6. Skills Check 6 VHDL 360 © After the loop finishes what will be the value of “count” signal? While count <10loop count <= count +1; Endloop;
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  • 11. For-Loop 10 VHDL 360 © Example 3: 8-bit shift register Library ieee; Use ieee.std_logic_1164.all; entityshift_registeris Port(clk, D, enable :inSTD_LOGIC; Q :outSTD_LOGIC); endentity; architecture Behavioral ofshift_registeris signalreg:std_logic_vector(7downto0); begin process(clk) begin ifrising_edge(clk)then if enable = '1' then reg(7)<= d; foriin7downto1loop reg(i-1)<=reg(i); endloop; endif; endif; endprocess; Q <=reg(0); end Behavioral;
  • 12. Exercise 1 The following diagram and flow chart show a “Serial In Parallel Out” register’s interface and describe how it behaves. 11 VHDL 360 ©
  • 13. Exercise 1 To complete the “Serial In Parallel Out” we need to do the following: Add necessary assignments to the reset condition Add a for loop to shift each bit of the internal register “reg” to the right Decide the condition by which the 8 queued values goes outside the register 12 VHDL 360 © libraryieee; useieee.std_logic_1164.all; useieee.std_logic_unsigned.all; entityserialinparalleloutis port(clk:instd_logic; d :instd_logic; rst:instd_logic; enable :instd_logic; ready :outstd_logic; q :outstd_logic_vector(7downto0)); endserialinparallelout;
  • 14. Exercise 1 architecture behave ofserialinparalleloutis signal count:std_logic_vector(2downto0); begin process(clk) variablereg:std_logic_vector(7downto0); begin ifrising_edge(clk)then ifrst= '1' then Q <= X"00";-- hexadecimal format <Here> else Ready <= '0'; if enable = '1' then < Add the loop Here> reg(7):= d; count <= count+1; … VHDL 360 © 13
  • 15. Exercise 1 … if count = ?? then Q <=reg; count <="000"; Ready <= '1'; endif; endif; endif; endif; endprocess; end behave; VHDL 360 © 14
  • 16. Sequential Statements Sequential Statements Case statement If statement loop statements While Loop For Loop Wait statement VHDL 360 © 15
  • 17. Wait Statement wait [ sensitivity clause ] [ condition clause ] [timeout clause] ; 16 VHDL 360 © Syntax: Process’ sensitivity list is only one means for controlling when a process is executed. Process execution can also be controlled with one or more waitstatements The wait statement causes suspension of a process Sensitivity clause, condition clause and timeout clause can optionally coexist in the same wait statement sensitivity_clause: onsignal_name Condition clause: until condition timeout_clause: fortime_expression Example 4: wait; -- suspends process forever waiton clock;-- suspends process execution until an event occurs on clock waitfor10 ns;-- suspends process execution for 10 ns waituntil A < B andenable = '1';-- suspends process until the condition is true waituntil A = '0' for2 ns;-- after A equals 0 wait 2 ns then resume execution of process
  • 18. Wait Statement Example 5: Counter generator 1 Architecture waveform oftestbenchis signal z :std_logic_vector(2downto0); Begin process-- no sensitivity list begin foriin0to7loop z <=conv_std_logic_vector(i,3);-- converts integer to std_logic_vector waitfor20 ns; endloop; wait; Endprocess; Endarchitecture; 17 VHDL 360 ©
  • 19. Skills Check Architecture waveform oftestbenchis signal z :std_logic_vector(2downto0); Begin process begin foriin0to7loop z <=conv_std_logic_vector(i,3); waitfor20 ns; endloop; -- wait; Endprocess; Endarchitecture; 18 VHDL 360 © What will happen if we remove this “wait”?
  • 20. Skills Check (Soln.) Architecture waveform oftestbenchis signal z :std_logic_vector(2downto0); Begin process begin foriin0to7loop z <=conv_std_logic_vector(i,3); waitfor20 ns; endloop; -- wait; Endprocess; Endarchitecture; 19 VHDL 360 © The waveform will not stop when Z reaches “111”, Z will start over again from “000”
  • 21.
  • 22. After fixing the problems, draw the waveforms
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  • 25.
  • 26. Conversion Functions 25 VHDL 360 © Reference page Syntax: conv_integer() Converts a std_logic_vector type to an integer; Requires: library ieee; use ieee.std_logic_unsigned.all; Or use ieee.std_logic_signed.all; conv_integer(std_logic_vector); Example 6: libraryieee; useieee.std_logic_unsigned.all; signal tour:std_logic_vector(3downto0); signal n:integer; n <=conv_integer(tour);
  • 27. Conversion Functions 26 VHDL 360 © Reference page conv_std_logic_vector() Converts an integer type to a std_logic_vector type Requires: library ieee; use ieee.std_logic_arith.ALL; Syntax: conv_std_logic_vector(integer, number_of_bits) Example 7: libraryieee; useieee.std_logic_arith.all; signal tour:std_logic_vector(3downto0); signal n:integer; tour <=conv_std_logic_vector(n,4);
  • 29. Lab work Write the code for a Fibonacci sequence generator: Output is the sum of the two previous outputs (0,1,1,2,3,5,8,13,…) Port names & types must be: Clk, rst: std_logic Fib_out : integer Don’t use inoutports rst: synchronous reset 28 VHDL 360 ©
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  • 31. Contacts You can contact us at: http://www.embedded-tips.blogspot.com/ VHDL 360 © 30