Ce diaporama a bien été signalé.
Nous utilisons votre profil LinkedIn et vos données d’activité pour vous proposer des publicités personnalisées et pertinentes. Vous pouvez changer vos préférences de publicités à tout moment.

Pythonによるカスタム可能な高位設計技術 (Design Solution Forum 2016@新横浜)

2 740 vues

Publié le

Pythonによるカスタム可能な高位設計技術 (Design Solution Forum 2016@新横浜)

Publié dans : Technologie
  • Identifiez-vous pour voir les commentaires

Pythonによるカスタム可能な高位設計技術 (Design Solution Forum 2016@新横浜)

  1. 1. Python E-mail: takamaeda_at_ist_hokudai_ac_jp 2016 10 14 13:50-14:30 (40 ) Design Solution Forum 2016 FPGA Track
  2. 2. Veriloggen: Python RTL 2 Design Generator by Python from veriloggen import * m = Module('blinkled') clk = m.Input('CLK') led = m.Output('LED', 8) count = m.Reg('count', 32) m.Assign( led(count[31:24]) ) m.Always(Posedge(clk)( count( count + 1 ) ) hdl = m.to_verilog() print(hdl) blinkled CLK RST LED count assign always Veriloggen Object module blinkled ( input CLK, output [7:0] LED ); reg [31:0] count; assign LED = count[31:24]; always @(posedge CLK) begin count <= count + 1; end endmodule Verilog Source Code module input CLK input RST blinkled Verilog AST to_verilog() Verilog AST Generator Verilog Code Generator Run on Python Interpreter Verilog HDL Python Verilog HDL
  3. 3. Veriloggen is available! n GitHub l Veriloggen: https://github.com/PyHDI/veriloggen l PyCoRAM: https://github.com/PyHDI/PyCoRAM l Pyverilog: https://github.com/PyHDI/Pyverilog n PIP Python 3 $ pip install veriloggen $ pip install pyverilog $ pip install pycoram $ git clone https://github.com/PyHDI/veriloggen.git $ git clone https://github.com/PyHDI/Pyverilog.git $ git clone https://github.com/PyHDI/PyCoRAM.git
  4. 4. FPGA n FPGA l Microsoft Catapult (Bing) l Baidu Deep Learning, etc n HPC l Altera SDK for OpenCL Xilinx Vivado HLS/SDSoC 4
  5. 5. FPGA in Datacenters n Microsoft Bing Search Engine (Catapult) l More space density and energy efficiency than GPU for machine learning (DNN) 5 Putnam+, A Reconfigurable Fabric for Accelerating Large-Scale Datacenter Services, ISCA'14 http://archive.eetindia.co.in/www.eetindia.co.in/STATIC/ARTIC LE_IMAGES/201408/EEIOL_2014AUG14_PL_NT_01_03.jpg
  6. 6. FPGA for low-cost and energy-efficiency 6 http://www.wired.com/2014/06/microsoft-fpga/ Agile Co-Design for a Reconfigurable Datacenter, FPGA'16
  7. 7. Phenox: FPGA-based quadcopter n Programmable drone system with FPGA l Zynq: SoC FPGA (ARM CPU + FPGA logics in a single chip) ü Easy to realize software with dedicated hardware support 7 Phenox http://phenoxlab.com/
  8. 8. n : RTL (Register Transfer Level) l l Timed l 8
  9. 9. 2 (c += a * b) 9 RTL (Verilog HDL): 105 2098 15
  10. 10. 2 (c += a * b) 10 RTL (Verilog HDL): 105 2098 15 L
  11. 11. n : RTL (Register Transfer Level) l l Timed l n : HLS: High Level Synthesis l l Untimed ü ü (Directive) l 11
  12. 12. 2 (c += a * b) 12 (C ): 11 163 1 →1/10 1/15
  13. 13. 2 (c += a * b) 13 (C ): 11 163 1 →1/10 1/15 J
  14. 14. Xilinx Vivado HLS n Free (≠Open-source) compiler for Xilinx FPGAs l Synthesize Verilog HDL/VHDL from C/C++ l Eclipse-based IDE 14Xilinx UG902
  15. 15. Altera OpenCL n OpenCL: parallel programming language for heterogeneous platforms n Synthesize Host-SW & FPGA-HW at same time, like GPU 15 http://www.bdti.com/InsideDSP/2013/02/13/Altera
  16. 16. OK n No. n l I/F n RTL l l n : RTL l Chisel [Bachrach+,DAC'12] l PyMTL [Lockhart+,MICRO’14] l Synthesijer.Scala [ ,IEICE RECONF'15] 16
  17. 17. Veriloggen: Python RTL 17 Design Generator by Python from veriloggen import * m = Module('blinkled') clk = m.Input('CLK') led = m.Output('LED', 8) count = m.Reg('count', 32) m.Assign( led(count[31:24]) ) m.Always(Posedge(clk)( count( count + 1 ) ) hdl = m.to_verilog() print(hdl) blinkled CLK RST LED count assign always Veriloggen Object module blinkled ( input CLK, output [7:0] LED ); reg [31:0] count; assign LED = count[31:24]; always @(posedge CLK) begin count <= count + 1; end endmodule Verilog Source Code module input CLK input RST blinkled Verilog AST to_verilog() Verilog AST Generator Verilog Code Generator Run on Python Interpreter Verilog HDL Python Verilog HDL
  18. 18. Verilog 18 Module Python (m )Reg "count <= 0" "count==1023" If (m )Always Module
  19. 19. (to_verilog) n Module to_verilog() 19
  20. 20. L 20
  21. 21. n l l n Veriloggen Python l l Python 21
  22. 22. 22 RAM I/F
  23. 23. : 23 RAM I/F 2 I/F
  24. 24. n l always : Seq l always + : FSM l : dataflow.* l : simulation.* l AXI : types.bram, types.axi n HDL from_verilog l HDL Python l HDL 24
  25. 25. Seq: (always ) 25 Seq
  26. 26. FSM: 26 FSM
  27. 27. Dataflow: 27
  28. 28. Dataflow: 28
  29. 29. Dataflow: 29
  30. 30. 30
  31. 31. 31 J
  32. 32. Dataflow n RTL l ü I/O l ü n l HDL 32
  33. 33. types.bram: RAM 33 RAM RAM
  34. 34. types.axi: AXI 34 AXI
  35. 35. from_verilog: HDL 35 HDL
  36. 36. Before and After n l HDL 36
  37. 37. Veriloggen : n Veriloggen 2 l l Python Python n HPC/ l 37
  38. 38. (CPR) n n CPU l ü [1] n GPU l ü CheCUDA[2], CheCL[3] n FPGA l [4,5] 38 IP
  39. 39. FPGA 39 FPGA On-chip Bus Application HW Memory Controller FPGA DRAM CPR HW Context Manager Reg Reg Logic Logic Controller Throttling Software Interface Read/Write RAM RAM RAM PCI-express Host CPU PCIe On-chip Bus Mem Ctrl DRAM Core SATA Disk Core Backup/Restore HW RAM (FF)FPGA DRAM PCIe DRAM DRAM • • • • Bus I/F
  40. 40. HardCheck: CPR IP 40 Design Generator w/ Veriloggen from veriloggen import * m = Module('blinkled') clk = m.Input('CLK') rst = m.Input('RST') led = m.Output('LED', 8) # ... module blinkled // ... endmodule Verilog Source Code or blinkled CLK RST LED count assign always Veriloggen Object Veriloggen Verilog Reader CPR IP-core Parameter Resolver CPR Port Inserter CPR Unit Generator IP Packager Fixed Verilog w/o Parameter Consumer Verilog w/ CPR Ports Verilog w/ CPR Component Checkpointable Hardware Synthesis Framework Unimplemented Unimplemented Input: Normal Hardware Output: CPR Hardware Veriloggen Verilog HDL Veriloggen IP IP (AXI4/Avalon)
  41. 41. n RAM l RTL ü RAM 41 Reg Reg Reg Reg Logic RAM RAM M-Bus S-Bus User-logic Reg: Register M-Bus/S-Bus: Master/Slave Bus I/F RAM: On-chip Memory
  42. 42. IP 42 Reg Reg Reg Reg Logic RAM RAM M-Bus S-Bus SR SR SR SR ContextManager (Reader/Writer) DMA Ctrl M-Bus S-Bus M-Bus S-Bus SW I/F Logic Ctrl Logic Throttling CPR Shift Registers Intermediate Bus I/F User-logic
  43. 43. IP 43 Reg Reg Reg Reg Logic RAM RAM M-Bus S-Bus SR SR SR SR ContextManager (Reader/Writer) DMA Ctrl M-Bus S-Bus M-Bus S-Bus SW I/F Logic Ctrl Logic Throttling CPR Shift Registers Intermediate Bus I/F User-logic HW CPR HW SW
  44. 44. CPR HW 44 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 module blinkled # ( parameter WIDTH = 8 ) ( input CLK, input RST, output reg [WIDTH-1:0] LED ); reg [32-1:0] count; always @(posedge CLK) begin if(RST) begin count <= 0; end else begin if(count == 1023) begin count <= 0; end else begin count <= count + 1; end end end always @(posedge CLK) begin if(RST) begin LED <= 0; end else begin if(count == 1023) begin LED <= LED + 1; end end end endmodule 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 module blinkled # ( parameter WIDTH = 8 ) ( input CLK, input RST, output reg [8-1:0] LED, input cpr_ctrl_read, input cpr_ctrl_write, output [8-1:0] cpr_read_LED, output [32-1:0] cpr_read_count, input [8-1:0] cpr_write_LED, input [32-1:0] cpr_write_count ); reg [32-1:0] count; always @(posedge CLK) begin if(RST) begin count <= 0; Restore Restore Port Backup Port Control Port always
  45. 45. CPR HW 45 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 module blinkled # ( parameter WIDTH = 8 ) ( input CLK, input RST, output reg [WIDTH-1:0] LED ); reg [32-1:0] count; always @(posedge CLK) begin if(RST) begin count <= 0; end else begin if(count == 1023) begin count <= 0; end else begin count <= count + 1; end end end always @(posedge CLK) begin if(RST) begin LED <= 0; end else begin if(count == 1023) begin LED <= LED + 1; end end end endmodule 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 output [8-1:0] cpr_read_LED, output [32-1:0] cpr_read_count, input [8-1:0] cpr_write_LED, input [32-1:0] cpr_write_count ); reg [32-1:0] count; always @(posedge CLK) begin if(RST) begin count <= 0; end else if(cpr_ctrl_write) begin count <= cpr_write_count; end else if(!cpr_ctrl_read) begin if(count == 1023) begin count <= 0; end else begin count <= count + 1; end end end always @(posedge CLK) begin if(RST) begin LED <= 0; end else if(cpr_ctrl_write) begin LED <= cpr_write_LED; end else if(!cpr_ctrl_read) begin if(count == 1023) begin LED <= LED + 1; end end end assign cpr_read_LED = LED; assign cpr_read_count = count; endmodule Restore Normal Behavior Restore Normal Behavior Backup Restore Port Backup Port always
  46. 46. RTL n parameter/localparam l ü generate for n l Veriloggen "Veriloggen.Resolver" parameter/localparam ü IP 46
  47. 47. Veriloggen.Resolver 47
  48. 48. Veriloggen is available! n GitHub l Veriloggen: https://github.com/PyHDI/veriloggen l PyCoRAM: https://github.com/PyHDI/PyCoRAM l Pyverilog: https://github.com/PyHDI/Pyverilog n PIP Python 48 $ pip install veriloggen $ pip install pyverilog $ pip install pycoram $ git clone https://github.com/PyHDI/veriloggen.git $ git clone https://github.com/PyHDI/Pyverilog.git $ git clone https://github.com/PyHDI/PyCoRAM.git
  49. 49. : Veriloggen: Python RTL 49 Design Generator by Python from veriloggen import * m = Module('blinkled') clk = m.Input('CLK') led = m.Output('LED', 8) count = m.Reg('count', 32) m.Assign( led(count[31:24]) ) m.Always(Posedge(clk)( count( count + 1 ) ) hdl = m.to_verilog() print(hdl) blinkled CLK RST LED count assign always Veriloggen Object module blinkled ( input CLK, output [7:0] LED ); reg [31:0] count; assign LED = count[31:24]; always @(posedge CLK) begin count <= count + 1; end endmodule Verilog Source Code module input CLK input RST blinkled Verilog AST to_verilog() Verilog AST Generator Verilog Code Generator Run on Python Interpreter Verilog HDL Python Verilog HDL

×