1. SMP IMPLEMENTATION ON
*BSD/MIPS
syuu1228

2. ∧ ∧
( ω ) ≡
( ≡
/ )
(/ ∪

3. MIPS
• MIPS
RISC
•

4. MIPS
• SGI
• DEC NEC
• Windows CE
NINTENDO64 PS PS2 PSP
• 1999 RISC 1/3 MIPS
• ARM

5. MIPS
BSD
• BSD MIPS NetBSD
Mach
• NetBSD 1.2 1996 DECstation
•
IIJ SEIL Juniper JunOS

6. MIPS SMP
• MIPS SMP
SGI
SGI Linux/MIPS
BSD
• SoC

7. MIPS
•
• Broadcom SiByte SB-1 Cisco
• Cavium Networks OCTEON
• 2010
• RMI XLR Processor/XLS Processor
• SONY PSP PSP CPU R4000×2
IO

8. BSD/MIPS SMP
• SGI BSD
SMP
• NetBSD Octane2
64bit 64bit
BSD OpenBSD OpenBSD
• CPU

9. SMP
• SMP SMP
•

10. OCTANE2
• CPU: R12000 400MHz 2MB L2 x 2
• RAM: 1024MB
• SCSI HDD
• 100BASE-T Ethernet

11. BSD/MIPS SMP
• CPU •
MP
•
•
• IPI
•
•
• MP
• MP , mutex
•

12. CPU
MP
• CPU cpu_info
• etc..
• MIPS
extern struct cpu_info cpu_info_primary;
#define
curcpu()
(&cpu_info_primary)
• CPU cpu_info curcpu()
MP

13. •
volatile intrmask_t cpl;
int splraise(int newcpl) {
int oldcpl;
__asm__ (" .set noreordern");
oldcpl = cpl;
cpl = oldcpl | newcpl;
__asm__ (" syncn .set reordern");
return (oldcpl);
}
• cpl cpu_info →curcpu()->ci_cpl
• (><;;

14. •
→
• cpu_info
•
CPU
•

15. MP ,
MUTEX
•
• spinlock
• atomic MIPS LL/SC
•
• MUTEX
• →
• mtx_enter(), mtx_try_enter()
•

16. • Q: extern int cnt; cnt++;
• A:
r0←cnt
r1←r0
r2←r1 + 1
r0 ←r2
• CPU CPU
•
LL/SC

17. LL/SC
r0←cnt
1:
r1←r0 LL
r2←r1 + 1
r0 ←r2 SC
if (!r0) goto 1

18. • CPU
•

19. IPI
•
cpu_unidle, signal, TLB shootdown
•
IPI: Inter-Processor Interrupt
•

20. •
•
•
•
•
• MP CPU
•

21. MP
•
•
→CPU TLB
• TLB
• →TLB Shootdown

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23. •
•
•
•
• CPU

24. •
•
•
•
•
→
•

26. • VM syuu1228
BSD/MIPS SMP, Plan9, KVM, UNIX etc...
, http://bit.ly/67BvV
• KVM softlab
KVM , Intel-VT, AMD SVM,
http://bit.ly/lTFlw

27. • P2PSIP
OverlayWeaver, Genkidama, DHT, P2P,
, : http://bit.ly/phIp4
•
, , ,