This document provides an overview of Marco Novati's thesis on 1D and 2D bitstream relocation for partially dynamically reconfigurable architectures. The aims are to create architectural support for online relocation of bitstreams in 1D and 2D and develop efficient relocation solutions suitable for the target system. An introduction is provided on reconfigurable computing and Xilinx FPGAs. Existing relocation approaches like PARBIT, BITPOS, BAnMaT and REPLICA are summarized. The proposed Polaris solutions are then outlined, including the Polaris workflow, YaRA target architecture, and proposed 1D and 2D relocation solutions using BAnMaT Lite, BiRF and BiRF Square.

1. 1D and 2D Bitstream Relocation for Partially Dynamically Reconfigurable Architecture BY Marco Novati [email_address] Thesis committee: Shantanu Dutt (chair), Marco Domenico Santambrogio, Piotr Gmytrasiewicz UIC Thesis Defense: May 8, 2008

10. Xilinx FPGAs and Configuration Memory

11. Frame Addressing: Virtex, Virtex-E * Inspired to Virtex Series Configuration Architecture User Guide

12. Frame Addressing: Virtex2pro * Taken from Virtex-II Pro and Virtex-II Pro X FPGA User Guide

14. Frame Addressing: Virtex 4-5 (2/2) * Inspired to Virtex 4 & 5 Configuration Architecture User Guide

17. Relocation: The Problem

18. Relocation: Scenario

19. Relocation: Motivation

28. Target Architecture: YaRA

29. PPC Based YaRA STATIC AREA

31. Configuration Bitstream

32. BiRF & BiRF Square Block Diagram

33. The Parser

37. Synthesis Results: Area FPGA BiRF BiRF Square Family Model Generic Version Optimized Version Generic Version Optimized Version Virtex II Pro vp7 11.6 % 3.6 % − − Virtex II Pro vp20 5.8 % 1.8 % − − Virtex II Pro vp30 4.2 % 1.3 % − − Virtex 4 vlx40 − − 2.2 % 0.9 % Virtex 4 vlx60 − − 1.5 % 0.6 % Virtex 4 vlx100 − − 0.8 % 0.3 % Virtex 5 vlx50 − − 1.1 % 0.8 % Virtex 5 vlx85 − − 0.6 % 0.4 % Virtex 5 vlx110 − − 0.5 % 0.3 %

41. Relocation Time Results (1/4)

43. Relocation Time Results (3/4)

44. Relocation Time Results (4/4)

49. Questions