This document provides resources for learning about the semiconductor industry, including conferences, papers, tutorials and courses. It aims to help readers achieve productivity, learn new things, share information, and gain concise knowledge. The resources cover topics like static and dynamic power analysis, memory macros, verification, low power design, and more. The document is intended to be updated weekly with additional learning materials.
IESVE Software for Florida Code Compliance Using ASHRAE 90.1-2019
Vlsi best notes google docs
1. I am preparing this document to help others in the semiconductor industry to achieve:
1. productivity
2. learn new things
3. share information
4. remove noise and share the most important, relevant and concise information
If you have any questions feel free to reach me @ mvrajesh1@gmail.com
I plan to update this document every week and share it with the world
This document is a working document, what I learned every day, I made a summary of those in here.
Last updated: March 17, 2019
https://www.edn.com/electronicsblogs/edapowerup/4430406/RailanalysisforSoCASICs
Static and Dynamic IR analysis on SoCs
This early analysis is important, because placement and routing engines consider the routing resources that
are left over after PG routing to be available for signal routing. So, late changes to PG routing can have a
domino effect on the signal routing, and also on placement, as PG routing can effectively “block” legal
placement locations, due to pin accessibility issues. In addition, the multipatterning routing that is required at
20nm and below further complicates late changes to PG routing, as the available legal routing outcomes are
more constrained and computationally much more intensive to achieve.
static rail analysis is driven by power consumption for the average situation, based on a switching probability
for each instance in the design. This approach allows for the computation of IR drops and current densities to
determine if the PG routing has a low enough resistance to deliver the required current for proper chip
operation, and sufficient widths and via instantiations to carry the current without electromigration failure.
Dynamic analysis outputs voltage waveforms that enable measurement of the transient droops or spikes at
points of interest in the PG networks. This approach enables us to determine whether or not the decoupling
capacitance between the power and ground networks is sufficient to keep these deviations to an acceptable
level.
Handling Memories and Other Macros
As in the static case, a similar extension is needed. Current waveforms must be characterized at different
physical points in the power pin geometries to account for local differences in current consumption due to
spatial differences in circuit behavior. For example, in the case of an SRAM, the current signatures over the bit
cells will be different from those over column drivers or row decoders. Thus, each macro will be represented by
multiple current source waveforms for the dynamic rail analysis circuit formulation.
SNUG conference every year:
https://www.synopsys.com/community/snug.html
Attend to socialize and meet other leaders from semiconductor industry
Interesting practical ideas in the presentations while implementing complex SoCs
Different tracks for verification, IP, PD etc.
TSMC Technology Symposium
https://www.tsmc.com/english/event/symp2019/index.html
Get to know the latest of what Fab is offering
Meet and socialize with other Semiconductor leaders
ISPD conference happens every year:
http://www.ispd.cc/?page=archives
Rich set of slides archived relevant to PD
Many of the advanced concepts are presented by University professors in a well defined manner
Front end RTL Design, verification, CDC trainings:
http://www.sunburstdesign.com/papers/
Take these trainings for a detailed and comprehensive knowledge on the topics of interest
UVM, System Verilog, CDC, Verification techniques
2. https://www.ucscextension.edu/certificateprogram/technology/vlsiengineering
I personally took a lot of classes in UCSC extension to broaden my areas of expertise
I took DFT, Systemverilog, STA, PD, Perl, Python, Machine Learning courses here, the classes are after hours
or on weekends and many professionals attend these courses
You can take one course per quarter
The location is very convenient to working professionals in bay area
https://scpd.stanford.edu/public/category/courseCategoryCertificateProfile.do?method=load&certificateId=1222198
there are courses which Stanford offers for working professionals
These require more time commitment
To study about chip variation (OCV), I took a lot of time to prepare these slides, you can read up on these slides:
https://www.slideshare.net/venkatamekala1/studyofinterandintrachipvariations
https://www.hotchips.org/archives/2010s/hc29/
These are some awesome technical presentations on various Chips designed from several industry leaders
I highly recommend watching these presentations
If possible attend Hot Chips conference some time to get a feel of it and also meet the best people in the
industry
http://www.hotchips.org/
https://www.youtube.com/channel/UCjtg76lhmVr0K86zMxbFGw
subscribe to hotchipvideos to listen to them in free time on youtube
Learn TCL
https://www.tcl.tk/
https://www.tcl.tk/man/tcl8.5/tutorial/tcltutorial.html
Nice tutorial for TCL programming
http://www.beedub.com/book/tkbook.pdf
Practical programming in TCL/TK
https://solvnet.synopsys.com/
enroll in solvnet (Synopsys)
There are many good articles and comprehensive documentation on all Synopsys tools
I highly recommend to read Design manuals, user guides of tools of your interest
https://www.synopsys.com/support/training.html
Attend these trainings on synopsys tools
http://users.ece.utexas.edu/~mcdermot/vlsi2/Lecture_8.pdf
Clock skew and jitter paper good read
http://koreatest.or.kr/sub02/2014data/3.pdf
Best paper on the timing margins
Read it thoroughly few times
http://sliponline.org/SLIP06/Presentations/2_1_lou.pdf
Download and read about interconnect on chip variation
Learn Linux commands especially sed, awk:
https://catonmat.net/archive
There are lot of online resources and it is not a one day sprint, keep learning daily as much as possible
7. TCL commands index:
https://www.tcl.tk/man/tcl8.6/TclCmd/contents.htm
http://csg.csail.mit.edu/6.823/lecnotes.html
MIT comp arch slides
http://csg.csail.mit.edu/pubs/courses.html
nice MIT courses
clock dividebyn algorithm:
https://www.slideshare.net/DeepakFloria/dividebynclock
https://www.youtube.com/watch?v=J8jJrNxthKA
timing exceptions tutorial xilinx, excellent
These are a series of videos, watch them for sure !
Textbook purely focused on congestion:
https://pure.tue.nl/ws/files/3334308/200911890.pdf
http://courses.ece.ubc.ca/579/WireShieldingSpacing.pdf
very good paper on crosstalk
ICC2 PG planning slides:
https://solvnet.synopsys.com/retrieve/customer/application_notes/attached_files/2559014/PG_Optimization_With_Co
mposite_Patterns_v2.pdf
Dynamic Voltage (IR) Drop Analysis and Design Closure:
https://www.apacheda.com/system/files/Dynamic_Voltage_drop.pdf
Question:
What is the impact of metal fill on signal integrity analysis?
Answer:
There are two types of metal fill, floating fill and grounded fill. Both types of metal fill are considered during signal
integrity analysis.
● Floating fill does not completely shield the aggressor nets, so signal integrity effects are seen from its
neighbors.
● Grounded fill completely shields the aggressor nets, so it has less impact on signal integrity than floating fill.
However, grounded fill increases the coupling capacitance and therefore increases the total capacitance more
than floating fill.
Most foundries recommend floating fill earlier in the design flow because it is more difficult to ground the fill, which
requires tracking and connecting to the PG nets of the fill. You should get a recommendation from your foundry on
which type of fill to use because it depends on the process and the cost.
10. accurate timing constraints
better PLL for jitter margins
multibit flipflop to reduce clock power
custom/structural placement
SAIF based placement, Low Power Placement flow
memory placement, floorplanning affects placement, total net length
software scheduling (not virus)
SRAM selection sweep to change floorplan and reduce overall net length
leakage power
multi VT, multi drive strengths
leakage, area recovery
power gating (header/footer)
body bias
control LVT usage in PD (allow only % of LVT cells)
3sigma versus 2sigma corners, reduces yield but better leakage
characterized library at power corner (Scaling values are pessimistic)
https://m.eet.com/media/1121857/chapter2_clocks_resets03.pdf
synchronous, asynchronous reset good document
Perl Interview Questions:
https://www.tutorialspoint.com/perl/perl_interview_questions.htm
Difference between contact and via:
Contact is connection to source, drain or poly. While vias is used to make connection between two metal layers. Both
vias and contact are formed using metals. Vias are generally made of tungsten while contact is made using aluminum.
Difference between via array and stacked via: http://www.vlsiexpert.com/2017/12/vias.html
ISPD via pillar advantages presentation: http://www.ispd.cc/slides/2017/k3.pdf
ITRS workshop slides: https://www.dropbox.com/sh/vasm431o2okvs16/AACXQvDNQ5hgzT8Bt4C6xT22a?dl=0
https://www.synopsys.com/news/pubs/snug/2018/europe/ta01sharmacrimminspresuser.pdf
Design closure of a VPU
MOM vs MIM capacitor explanation:
https://www.quora.com/WhatisthestructureofaMIMcapacitor
http://www.ispd.cc/contests/19/lefdefref.pdf
LEF, DEF language reference document