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I am preparing this document to help others in the semiconductor industry to achieve: 
1. productivity 
2. learn new things 
3. share information 
4. remove noise and share the most important, relevant and concise information 
 
If you have any questions feel free to reach me @  mvrajesh1@gmail.com 
I plan to update this document every week and share it with the world 
This document is a working document, what I learned every day, I made a summary of those in here. 
Last updated: March 17, 2019 
 
https://www.edn.com/electronics­blogs/eda­power­up/4430406/Rail­analysis­for­SoC­ASICs 
­ Static and Dynamic IR analysis on SoCs 
­ This early analysis is important, because placement and routing engines consider the routing resources that 
are left over after PG routing to be available for signal routing. So, late changes to PG routing can have a 
domino effect on the signal routing, and also on placement, as PG routing can effectively “block” legal 
placement locations, due to pin accessibility issues. In addition, the multi­patterning routing that is required at 
20nm and below further complicates late changes to PG routing, as the available legal routing outcomes are 
more constrained and computationally much more intensive to achieve. 
­ static rail analysis is driven by power consumption for the average situation, based on a switching probability 
for each instance in the design. This approach allows for the computation of IR drops and current densities to 
determine if the PG routing has a low enough resistance to deliver the required current for proper chip 
operation, and sufficient widths and via instantiations to carry the current without electromigration failure. 
­ Dynamic analysis outputs voltage waveforms that enable measurement of the transient droops or spikes at 
points of interest in the PG networks. This approach enables us to determine whether or not the decoupling 
capacitance between the power and ground networks is sufficient to keep these deviations to an acceptable 
level. 
­ Handling Memories and Other Macros 
­ As in the static case, a similar extension is needed. Current waveforms must be characterized at different 
physical points in the power pin geometries to account for local differences in current consumption due to 
spatial differences in circuit behavior. For example, in the case of an SRAM, the current signatures over the bit 
cells will be different from those over column drivers or row decoders. Thus, each macro will be represented by 
multiple current source waveforms for the dynamic rail analysis circuit formulation. 
SNUG conference every year: 
https://www.synopsys.com/community/snug.html 
­ Attend to socialize and meet other leaders from semiconductor industry 
­ Interesting practical ideas in the presentations while implementing complex SoCs 
­ Different tracks for verification, IP, PD etc. 
TSMC Technology Symposium 
­ https://www.tsmc.com/english/event/symp2019/index.html 
­ Get to know the latest of what Fab is offering 
­ Meet and socialize with other Semiconductor leaders 
ISPD conference happens every year: 
http://www.ispd.cc/?page=archives 
­ Rich set of slides archived relevant to PD 
­ Many of the advanced concepts are presented by University professors in a well defined manner 
Front end RTL Design, verification, CDC trainings: 
http://www.sunburst­design.com/papers/ 
­ Take these trainings for a detailed and comprehensive knowledge on the topics of interest 
­ UVM, System Verilog, CDC, Verification techniques 
https://www.ucsc­extension.edu/certificate­program/technology/vlsi­engineering 
­ I personally took a lot of classes in UCSC extension to broaden my areas of expertise 
­ I took DFT, Systemverilog, STA, PD, Perl, Python, Machine Learning courses here, the classes are after hours 
or on weekends and many professionals attend these courses 
­ You can take one course per quarter 
­ The location is very convenient to working professionals in bay area 
https://scpd.stanford.edu/public/category/courseCategoryCertificateProfile.do?method=load&certificateId=1222198 
­ there are courses which Stanford offers for working professionals 
­ These require more time commitment 
To study about chip variation (OCV), I took a lot of time to prepare these slides, you can read up on these slides: 
https://www.slideshare.net/venkatamekala1/study­of­inter­and­intra­chip­variations 
 
https://www.hotchips.org/archives/2010s/hc29/ 
­ These are some awesome technical presentations on various Chips designed from several industry leaders 
­ I highly recommend watching these presentations  
­ If possible attend Hot Chips conference some time to get a feel of it and also meet the best people in the 
industry 
­ http://www.hotchips.org/ 
­  
 
https://www.youtube.com/channel/UCjtg­76lhmVr0K86zMxbFGw 
­ subscribe to hotchipvideos to listen to them in free time on youtube 
Learn TCL 
­ https://www.tcl.tk/ 
­ https://www.tcl.tk/man/tcl8.5/tutorial/tcltutorial.html 
­ Nice tutorial for TCL programming 
­ http://www.beedub.com/book/tkbook.pdf 
­ Practical programming in TCL/TK 
https://solvnet.synopsys.com/ 
­ enroll in solvnet (Synopsys) 
­ There are many good articles and comprehensive documentation on all Synopsys tools 
­ I highly recommend to read Design manuals, user guides of tools of your interest 
­ https://www.synopsys.com/support/training.html 
­ Attend these trainings on synopsys tools 
http://users.ece.utexas.edu/~mcdermot/vlsi­2/Lecture_8.pdf 
Clock skew and jitter paper ­ good read 
http://koreatest.or.kr/sub02/2014data/3.pdf 
­ Best paper on the timing margins 
­ Read it thoroughly few times 
 
http://sliponline.org/SLIP06/Presentations/2_1_lou.pdf 
­ Download and read about interconnect on chip variation 
Learn Linux commands especially sed, awk:  
https://catonmat.net/archive 
­ There are lot of online resources and it is not a one day sprint, keep learning daily as much as possible 
 
So much detailed and in­depth presentation of FinFet technology: 
https://people.eecs.berkeley.edu/~tking/presentations/KingLiu_2012VLSI­Tshortcourse 
 
Another super article on timing margins, OCV: 
http://www.tauworkshop.com/2014/Slides/hill_tau_2014_shared.pdf 
 
There are some VLSI videos taught by this professor, they are quite basic and fundamental but are taught very well, 
watch these videos: 
https://www.youtube.com/playlist?list=PLFhizsGPFKt8gz­bYlKMDCgBKwxMc33H2 
 
Xilinx timing closure user guide: 
http://www­wjp.cs.uni­saarland.de/lehre/hadeprak/block_ss15/Upload/ug612.pdf 
 
Excellent thesis on clock tree design: 
https://www2.eecs.berkeley.edu/Pubs/TechRpts/2008/EECS­2008­98.pdf 
­ I often find reading M.S. or PhD thesis papers are very refreshing, detailed and gives you a perspective on a 
particular topic at a whole new level 
­ Keep reading PhD/Master’s thesis presentations when you have free time 
Some of the SNUG user presentations are here: 
https://www.synopsys.com/community/snug/snug­austin/location­proceedings­2015.html 
­ 2015 SNUG presentations 
­ These are very helpful to know up­to­date of semiconductor industry happenings 
UPF standards document: 
http://citeseerx.ist.psu.edu/viewdoc/download?doi=10.1.1.133.6194&rep=rep1&type=pdf 
 
Design Verification Conference: 
­ https://dvcon.org/ 
 
What is dark silicon? 
­ https://en.wikipedia.org/wiki/Dark_silicon 
 
GCA (Galaxy Constraint Analyzer) 
­ https://www.synopsys.com/news/pubs/snug/sanjose11/tc3_tutorial_GCA_FINAL.pdf 
 
Global Routing and Detailed Routing (Few slides focused on this topic) 
http://cc.ee.ntu.edu.tw/~ywchang/Courses/PD_Source/EDA_routing.pdf 
 
Low Power Design Techniques (Good Slides): 
http://www.ee.ncu.edu.tw/~jfli/vlsi21/lecture/ch04.pdf 
 
SystemVerilog for Design (Textbook download): 
http://read.pudn.com/downloads166/sourcecode/math/758655/Springer%20­%20SystemVerilog%20for%20Design,%2
02nd%20Edition.pdf 
 
HDL methods for low power design: 
https://www.design­reuse.com/articles/20775/hdl­design­low­power.html 
 
Principles of verifiable RTL design: 
https://pdfs.semanticscholar.org/11d0/1cbdd90177c882bfa029879c48d0cbd3a4a9.pdf 
 
Serdes PAM4 presentation: 
https://www.xilinx.com/publications/events/designcon/2016/slides­pam4signalingfor56gserial­zhang­designcon.pdf 
 
Thesis presentations from UC Berkeley: 
https://www2.eecs.berkeley.edu/Pubs/TechRpts/ 
 
https://vlsicad.ucsd.edu/Presentations/talk/EDPS2015_Kahng­distributed.pdf 
­ A Roadmap for Low­Power Design: Trends, Technology, Tools 
 
http://web.stanford.edu/class/archive/ee/ee371/ee371.1066/lectures/Old/Older/lect_09_power_delivery_1up.pdf 
­ Lecture from a course in Stanford university on power delivery on Chip 
 
Write constraints for synthesis tutorial: ***** 
http://www.ee.bgu.ac.il/~digivlsi/slides/synopsys_class_2_5_1.pdf 
 
Memory Errors in Modern Systems The Good, The Bad, and The Ugly 
­ https://www.cs.virginia.edu/~gurumurthi/papers/asplos15.pdf 
 
VLSI interview questions: 
https://cdcnitw.files.wordpress.com/2013/04/vlsi_questions.pdf 
 
https://www.edn.com/design/test­and­measurement/4388547/SOC­DFT­verification­with­static­analysis­and­formal­m
ethods 
­ SOC DFT verification with formal methods 
 
Understanding the I2C bus protocol: 
http://www.ti.com/lit/an/slva704/slva704.pdf 
 
Undestanding LVS (Layout versus Schematic): 
https://www.edn.com/design/integrated­circuit­design/4418390/An­insight­into­layout­versus­schematic 
https://en.wikipedia.org/wiki/Layout_Versus_Schematic 
 
 
Marketing slide on implementing Deep Learning Chips: 
https://www.synopsys.com/designware­ip/technical­bulletin/implementing­high­performance­deep­learning­2018q1.ht
ml?elq_mid=9766&elq_cid=763198 
 
Machine Learning Glossary: 
https://developers.google.com/machine­learning/glossary/ 
­ Explore ! 
 
3D IC packaging technology: 
http://s3.amazonaws.com/sdieee/1817­SanDiegoCPMTDL_Lau_advancedpackaging.pdf 
­ Nice article covering all practical and implemented strategies on 3D IC packaging 
 
Awesome book on Python (Python tips !): 
http://book.pythontips.com/en/latest/index.html 
pickle in python: 
https://pythontips.com/2013/08/02/what­is­pickle­in­python/ 
https://docs.python.org/2/library/pickle.html 
Python tutorial read at:  https://docs.python.org/2/tutorial/ 
List Comprehensions Python:  https://docs.python.org/3/tutorial/datastructures.html#list­comprehensions 
Object Oriented Programming in Python tutorial:  http://www.tutorialspoint.com/python/python_classes_objects.htm 
 
hotchips End of Moores Law presentation from DARPA 
https://www.youtube.com/watch?v=JpgV6rCn5­g 
 
Good coursework on VLSI Design Flow: 
https://www.csee.umbc.edu/~tinoosh/cmpe641/ 
 
Writing Timing constraints in primetime in SDC format:  
https://trilobyte.com/pdf/golson_snug09.pdf 
https://www.synopsys.com/news/pubs/snug/2016/silicon­valley/tb05­2­swamy­pres­user.pdf 
 
Power Gate Optimization Method for In­Rush Current and Power Up Time 
https://dac.com/sites/default/files/App_Content/files/48/48_07U_1.pdf 
  
Reliable Silicon Qualification of Standard Cell and IP's Using Synopsys OCC 
https://www.synopsys.com/news/pubs/snug/2016/silicon­valley/tb03­2­juneja­paper.pdf 
 
Video on understanding UPF standard (nice intro video): 
https://www.youtube.com/watch?v=UJA0liTwDCw&t=1551s 
 
Introduction to Algorithms (Best book on algorithms): 
http://ressources.unisciel.fr/algoprog/s00aaroot/aa00module1/res/%5BCormen­AL2011%5DIntroduction_To_Algorith
ms­A3.pdf 
 
tmux tutorial on github: 
https://gist.github.com/MohamedAlaa/2961058 
 
Sample python programs (Awesome): 
https://pythonspot.com/ 
 
Modules Python: 
https://docs.python.org/3/tutorial/modules.html 
 
Iterators and Generators Python: 
https://anandology.com/python­practice­book/iterators.html 
 
Default arguments ­ stick concept and functions nested loops: 
http://effbot.org/zone/default­values.htm 
 
difference between static method and class method: 
https://stackoverflow.com/questions/136097/what­is­the­difference­between­staticmethod­and­classmethod­in­python 
 
regular expressions python: 
https://docs.python.org/3.4/library/re.html 
 
Python Pandas: 
https://github.com/pandas­dev/pandas/blob/master/doc/cheatsheet/Pandas_Cheat_Sheet.pdf 
 
 
https://pandas.pydata.org/ 
 
flicker: 
http://www.imagemagick.org/Usage/scripts/flicker_cmp 
 
http://www.vlsi­expert.com/2017/12/vias.html 
­­ Nice article on via array and stacked via concept 
http://www.ee.iitm.ac.in/~ee09d017/ee7030_general.html 
­ IITM lecture notes 
 
www.edn.com 
­ lot of good articles to read 
 
TCL commands index: 
https://www.tcl.tk/man/tcl8.6/TclCmd/contents.htm 
 
http://csg.csail.mit.edu/6.823/lecnotes.html 
­ MIT comp arch slides 
http://csg.csail.mit.edu/pubs/courses.html 
­ nice MIT courses 
 
clock divide­by­n algorithm: 
https://www.slideshare.net/DeepakFloria/divide­by­n­clock 
 
 
https://www.youtube.com/watch?v=J8jJrNxthKA 
­ timing exceptions tutorial xilinx, excellent 
­ These are a series of videos, watch them for sure ! 
 
Textbook purely focused on congestion: 
https://pure.tue.nl/ws/files/3334308/200911890.pdf 
 
http://courses.ece.ubc.ca/579/WireShieldingSpacing.pdf 
­ very good paper on crosstalk 
 
ICC2 PG planning slides: 
https://solvnet.synopsys.com/retrieve/customer/application_notes/attached_files/2559014/PG_Optimization_With_Co
mposite_Patterns_v2.pdf 
 
Dynamic Voltage (IR) Drop Analysis and Design Closure: 
https://www.apache­da.com/system/files/Dynamic_Voltage_drop.pdf 
 
Question: 
What is the impact of metal fill on signal integrity analysis? 
Answer: 
There are two types of metal fill, floating fill and grounded fill. Both types of metal fill are considered during signal 
integrity analysis. 
● Floating fill does not completely shield the aggressor nets, so signal integrity effects are seen from its 
neighbors. 
● Grounded fill completely shields the aggressor nets, so it has less impact on signal integrity than floating fill. 
However, grounded fill increases the coupling capacitance and therefore increases the total capacitance more 
than floating fill. 
Most foundries recommend floating fill earlier in the design flow because it is more difficult to ground the fill, which 
requires tracking and connecting to the PG nets of the fill. You should get a recommendation from your foundry on 
which type of fill to use because it depends on the process and the cost. 
 
 
good explanation of max_cap, max_trans etc. 
http://www.vlsi­expert.com/2012/02/design­constraint­maximum­and­minimum.html 
 
good Basic refresher course on RTL design: 
http://academic.csuohio.edu/chu_p/rtl/chu_rtL_book/silde/ 
 
basic info on routing: 
https://www.slideshare.net/NaveenKumar11/vlsi­routing?from_action=save 
 
 
 
 
 
https://www.edn.com/design/test­and­measurement/4386191/Launch­off­shift­at­speed­test 
 
Clock Enable Timing Methodology:  http://www.ispd.cc/slides/2013/7_dangat.pdf 
 
https://solvnet.synopsys.com/retrieve/015769.html?otSearchResultSrc=advSearch&otSearchResultNumber=2&otPag
eNum=1 
­ clock gating checks, awesome article 
 
 
set_output_delay ­min 
 
For more clarification Read this 
 
The data setup time is the time the data inputs must be valid before the clock/strobe signal occurs. The hold time is 
the time the data must remain valid after the clock/strobe. Both can be zero or negative. An example is that t_SHDI ­ 
the data hold time after DS* is high is 0. A zero setup time means that the time for the data to propagate within the 
component and load into the latch is less than the time for the clock to propagate and trigger the latch. A zero hold 
time means either that the moment the clock is asserted, the latch no longer looks at its inputs, or else that the clock 
path delay is shorter than the data path delay. A negative setup or hold time means that there is an even larger 
difference in path delays, so that even if the data is sent later than the clock (for setup time), it still arrives at the latch 
first. Typically manufacturers avoid specifying negative values since this restricts later design and manufacturing 
decisions, but they often specify zero values since this simplifies usage in a system. 
https://www.intel.com/content/dam/altera­www/global/en_US/pdfs/literature/an/an433.pdf 
­ source synchronous constraints 
 
constraining data skew check in the .lib 
­ http://tech.tdzire.com/how­to­constrain­the­data­skew­check­in­the­lib/ 
 
DDR timing in primetime 
http://www.zimmerdesignservices.com/mydownloads/snug02_ddr_final032406.pdf 
http://www.zimmerdesignservices.com/publications/ 
 
 
low power design techniques 
­ dynamic power 
­ reduce toggle count 
­ RTL clock gating and ICGs 
­ reduce voltage 
­ structural placement 
­ reduce cell drive strengths 
­ VT sweep to achieve best subset of cells for timing closure and lower power 
­ reduce glitches 
­ reduce total net length 
­ multiple modes (different vdd, different frequency) 
­ split rails (VDD_mem, VDD_logic) 
­ relax max_trans constraint 
­ disable high drive strength cells meeting timing 
­ disable complex cells 
­ retiming? 
­ technology node selection 
­ voltage islands 
­ low power designware components 
­ clock tree quality (latency, skew) 
­ accurate timing constraints 
­ better PLL for jitter margins 
­ multibit flip­flop to reduce clock power 
­ custom/structural placement 
­ SAIF based placement, Low Power Placement flow 
­ memory placement, floorplanning affects placement, total net length 
­ software scheduling (not virus) 
­ SRAM selection sweep to change floorplan and reduce overall net length 
­ leakage power 
­ multi VT, multi drive strengths 
­ leakage, area recovery 
­ power gating (header/footer) 
­ body bias 
­ control LVT usage in PD (allow only % of LVT cells) 
­ 3­sigma versus 2­sigma corners, reduces yield but better leakage 
­ characterized library at power corner (Scaling values are pessimistic) 
­  
 
 
https://m.eet.com/media/1121857/chapter2_clocks_resets­03.pdf 
­ synchronous, asynchronous reset good document 
 
Perl Interview Questions: 
https://www.tutorialspoint.com/perl/perl_interview_questions.htm 
 
Difference between contact and via: 
Contact is connection to source, drain or poly. While vias is used to make connection between two metal layers. Both 
vias and contact are formed using metals. Vias are generally made of tungsten while contact is made using aluminum.  
 
Difference between via array and stacked via:  http://www.vlsi­expert.com/2017/12/vias.html 
 
ISPD via pillar advantages presentation:  http://www.ispd.cc/slides/2017/k3.pdf 
 
ITRS workshop slides:  https://www.dropbox.com/sh/vasm431o2okvs16/AACXQvDNQ5hgzT8Bt4C6xT22a?dl=0 
 
https://www.synopsys.com/news/pubs/snug/2018/europe/ta­01­sharma­crimmins­pres­user.pdf 
­ Design closure of a VPU 
 
MOM vs MIM capacitor explanation: 
https://www.quora.com/What­is­the­structure­of­a­MIM­capacitor 
 
 
http://www.ispd.cc/contests/19/lefdefref.pdf 
­ LEF, DEF language reference document 
 
Why a delay cell for hold fixing? explanation: 
https://www.design­reuse.com/articles/38949/hold­fixing­techniques.html 
 
 
 
Register Banking basic explanation: 
http://vlsi­soc.blogspot.com/2016/09/register­banking.html 
 
Resolving methodology issues in 7nm: 
https://www.synopsys.com/news/pubs/snug/2018/india/wa1­02­maity­pres­user.pdf 
 
 
excellent article by TSMC founder in ISPD: 
http://www.ispd.cc/slides/2017/k3.pdf 
 
Naweed Sherwani’s algorithms for VLSI Design Automation text book download: 
https://doc.lagout.org/science/0_Computer%20Science/2_Algorithms/Algorithms%20for%20VLSI%20Physical%20Des
ign%20Automation%20%283rd%20ed.%29%20%5BSherwani%201998­11­30%5D.pdf 
 
regexp explanation TCL: 
https://www.tcl.tk/man/tcl8.5/tutorial/Tcl20.html 
https://wiki.tcl­lang.org/page/split 
https://wiki.tcl­lang.org/page/comment 
 
 
 
 
 
dict examples TCL: 
http://www.wellho.net/mouth/3614_Tcl­dicts­a­tutorial­and­examples.html 
set demo {A 1 B 2 C { 3 4 } D 5} 
set no [dict get $demo B] 
puts $no 
 
set no [lindex $demo 3] 
 
foreach item [dict keys $demo] { 
set val [dict get $demo $item] 
puts “Key: $item , Value: $val” 
} 
 
dict for {thekey thevalue} $demo { 
puts “Key: $thekey , Value: $thevalue” 
} 
 
set dict1 {A 1 B 2 C 3} 
set dict2 {C 4 D 5 E 6} 
dict lappend dict2 F 7 
 
set dict3 [dict merge $dict1 $dict2] 
 
dict lappend dict3 G 8 
dict lappend dict3 H 9 
  
dict append dict3 H 000 
 
set remove_dict [dict remove $dict3 B] 
 
set replace_dict [dict replace $dict3 C 700] 
 
timetable original $dict3 
timetable modified $dict3 
timetable “before 8am” $dict3 
 
set short_dict [dict filter $dict3 value {6}] 
 
set sz [dict size $dict3] 
 
dict create  ­ create a new dictionary 
dict append  ­ append a string to a value in a dictionary 
dict lappend  ­ add a new key, value pair to a dictionary 
dict merge  ­ concatenate two dictionaries, but remove duplicate keys 
dict remove  ­ remove a pair based on its key 
dict replace  ­ replace a value based on its key 
dict filter  ­ return a small dictionary based on a match to a key or a value 
dict size  ­ tell me how many pairs there are in a dictionary 
dict incr  ­ to increment a value within a dict. Very useful indeed for counters 
dict info  ­ information string about the dict 
dict exists  ­ to check whether a key exists 
 
dict set DB Science assignment1 20 
dict set DB Science assignment2 40 
dict set DB Maths assignment1 30 
dict set DB Social assignment1 40 
dict set DB Social assignment2 50 
dict set DB Social assignment3 10 
 
dict for {thekey thevalue} $DB { 
puts “$thekey Subject:” 
dict with levels { 
puts “First Level $assignment1” 
puts “Second Level $assignment2” 
if { [dict exists $DB $subject “assignment3”] } { 
puts “assignment3 exists” 
} else { 
puts “assignment3 does not exist” 
} 
} 
} 
 
http://www.wellho.net/mouth/3638_Sorting­dicts­and­arrays­in­Tcl.html 
array s are NOT simply formatted strings ­ they're a special structure which uses hashing techniques for managing the 
members, making it very fast for Tcl to access members by key, but meaning (on the down side) that you can only 
pass the whole array into a proc using  upvar , and that you cannot sort an array. So they're similar to  dict s in Python, 
and to hashes in Perl. 
 
dict s are formatted strings ­ so you can pass them directly into procs, and you can reorder them ­ but they're much 
less efficient that arrays once you start passing around and manipulating structures of significant size. Tcl's dicts are 
similar in many ways to associative arrays in PHP. 
 
If you want to output the contents of a dict, sorted, then much the easiest way up to and including release 8.5 of Tcl is 
to use  lsort  to sort a list of keys, then iterate through that list in sorted order. There's an example  [here]  on our web 
site. Should you wish to hold onto your sorted dict, then the best way to do it is to sort the keys and rebuild a new 
dictionary ­ I've also included that at the end of the example 
 
Once version 8.6 ofTcl gets to a production release (and you have it on all your systems), you'll be able to use the 
­stride  and  index  options on lsort, which will directly return you a sorted dict if you pass in a parameter 2 to the stride. 
Thus: 
  lsort ­stride 2 {grapefruit 10 banana 110 cherry 25} 
will return  
  banana 110 cherry 25 grapefruit 10 
and 
  lsort ­stride 2 ­index 1 ­integer {grapefruit 10 banana 110 cherry 25} 
wlll return 
  grapefruit 10 cherry 25 banana 110  
 
 
very good dictionary tutorial TCL: 
https://wiki.tcl­lang.org/page/Tcl+Tutorial+Lesson+23a 
Hierarchical test design: 
https://www.edn.com/electronics­blogs/test­voices/4430471/Hierarchial­test­improves­pattern­application­efficiency 
 
Clock distribution on multi­GHz processors: 
http://www.ewh.ieee.org/soc/cpmt/tc12/fdip03/mahoneyfoils.pdf 
 
Synchronizer techniques for multi clock domains: 
https://www.edn.com/electronics­blogs/day­in­the­life­of­a­chip­designer/4435339/Synchronizer­techniques­for­multi­cl
ock­domain­SoCs 
 
Dennard Scaling: 
https://www.rambus.com/blogs/understanding­dennard­scaling­2/ 
 
Embedded systems design: 
http://users.ece.utexas.edu/~mcdermot/2019_SPRING_EE445L/index.htm 
 
Awesome coursework from UTAustin: 
http://users.ece.utexas.edu/~mcdermot/ 
 
Library validation using liberate tool: 
https://www.cadence.com/content/cadence­www/global/en_US/home/tools/custom­ic­analog­rf­design/library­characte
rization/liberate­lv­library­validation­solution.html 
 
Thesis paper on GPIOs design: 
https://rc.library.uta.edu/uta­ir/bitstream/handle/10106/24772/Abraham_uta_2502M_12777.pdf?sequence=1 
 
TCD cell definition: 
https://vlsibasic.blogspot.com/2017/01/tcd­cell.html 
 
 
B2B diode ESD: 
1. http://www.ozeninc.com/wp­content/uploads/2015/05/ensuring­chip­level­esd­integrity.pdf 
 
 
­ codec insertion flow in DFT: 
http://tech.tdzire.com/codec­insertion­flow­using­synopsys­dft­compiler/ 
 
 
Memory design awesome slides: 
https://inst.eecs.berkeley.edu/~cs250/fa10/lectures/lec08.pdf 
 
Lot of posts on Machine Learning/AI: 
https://autome.me/artificial­intelligence?fbclid=IwAR0gTTTVdPvZqd62UX3HhuF0kzwXlQS7OKyY0s1w80ouHoxVpgtJ
t83k0uA 
 
Learn Screen: 
screen: 
https://linuxize.com/post/how­to­use­linux­screen/ 
 
STA basics slides good read: 
http://www.eng.biu.ac.il/temanad/files/2017/02/Lecture­3­STA.pdf 
 
Computer architecture videos (OLD): 
https://www.youtube.com/watch?list=PL5Q2soXY2Zi9JXe3ywQMhylk_d5dI­TM7&v=g3yH68hAaSk&app=desktop 
 
ML videos repository: 
https://www.artificial­intelligence.video/category/machine­learning­videos 
 
Best practices for high performance ARM cores on 7nm: (Awesome read) 
https://www.synopsys.com/news/pubs/snug/2018/europe/tb­01­gibbons­pres­snps.pdf 
 
Physical Interconnect Aware Network Optimizer: 
http://www.ispd.cc/slides/2018/s7_2.pdf 
 
Scaling of Machine Learning, Nvidia’s Bill Dally presentation: 
https://www.youtube.com/watch?time_continue=864&v=h3QKvUPg_AI 
 
Achieving routing convergence: Nice slides: 
https://www.synopsys.com/news/pubs/snug/2018/india/wa1­03­murugesan­pres­user.pdf 
 
AI creating new opportunities for chip designers: 
https://www.synopsys.com/news/pubs/snug/2018/europe/tc­06­tanurhan­pres­snps.pdf 
 
ML on FPGAs:  https://www.youtube.com/watch?v=3iCifD8gZ0Q 
 
 
corner based timing sign­off: 
http://anysilicon.com/wp­content/uploads/2014/10/Corner_based_Signoff_paper_Jan_2014a.pdf 
 
Few awesome videos on clocks and constraints: 
https://www.youtube.com/channel/UCFeMMgibcTMEMNcp_Qn7KsA/videos 
 
Main memory and DRAM system, CMU computer architecture lectures: 
https://www.youtube.com/watch?v=IUk9o9wvX1Y&feature=youtu.be 
 
Achieving correlation between synthesis and routed design for a high performance block: 
https://solvnet.synopsys.com/video/customer/application_notes/attached_files/2536710/tc2­1.mp4 
 
 

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