SlideShare une entreprise Scribd logo
1  sur  35
   Routing
   Routing Problem
   Routing Regions
   Types of Routing
    -Global Routing
    -Detailed Routing
   Conclusion
   References
o   The routing is to locate a set of wires in the routing space that
    connect all the nets in the net list. The capacities of channels,
    width of wires, and wire crossings often need to be taken into
    consideration .
   Apply after placement
   Input:
      Netlist

      Timing budget for, typically, critical nets

      Locations of blocks and locations of pins

   Output:
      Geometric layouts of all nets

   Objective:
      Minimize the total wire length, the number of vias, or just

       completing all connections without increasing the chip
       area.
      Each net meets its timing budget.
   For a multi-terminal net, we can construct a spanning
    tree to connect all the terminals together.
   But the wire length will be large.
   Better use Steiner Tree:
                                                            Steiner
       A tree connecting all terminals and some              Node
       additional nodes (Steiner nodes).
   Rectilinear Steiner Tree:

       Steiner tree in which all the edges run
       horizontally and vertically.
   Minimum Steiner Tree Problem:
       Given a net, find the steiner tree with the minimum
        length.
       This problem is NP-Complete!
   May need to route tens of thousands of nets simultaneously
    without overlapping.
   Obstacles may exist in the routing region.
Two phases:
Divide the routing area into routing regions of simple shape

(rectangular):                                Switchbox

      Channel



•   Channel: Pins on 2 opposite sides.

•   2-D Switchbox: Pins on 4 sides.

•   3-D Switchbox: Pins on all 6 sides.
Gate-Array   Standard-Cell   Full-Custom




                  Feedthrough Cell
Routing




                                           Detailed
      Global routing                        routing




                                      Channel         Switch Box
Line Routing     Maze Routing
                                      Routing           Routing
Placement
                                       Global routing

Generate a 'loose' route for each net
Assign a list of routing region to each net
without specifying the actual layout of
wires.

                                        Detailed routing

Find the actual geometry layout of each net
   with in the assigned routing regions




               Compaction
o   Minimize the total overflow
o   Minimize the total wire length
o   Minimize running time
Assign routing regions to each net. Need to consider timing
budget of nets and routing congestion of the regions.
Assign pins on routing region boundaries for each net.
(Prepare for the detailed routing stage for each region.)
Sequential Approach:
      Route the nets one at a time.
      Order dependent on factors like criticality, estimated wire
       length, etc.
      If further routing is impossible because some nets are
       blocked by nets routed earlier, apply Rip-up and Reroute
       technique.
      This approach is much more popular.
Concurrent Approach:
      The major drawback of the sequential approach is
       that it suffers from the net ordering problem.
      Consider all nets simultaneously.
      Can be formulated as an integer program.
   Given:
       A planar rectangular grid graph.
       Two points S and T on the graph.
       Obstacles modeled as blocked vertices.
   Objective:
       Find the shortest path connecting S and T.
   This technique can be used in global or detailed routing
    (switchbox) problems.
S              S
                              S 

         T     X             X    
                      T
               X             X       T

Area Routing   Grid Graph     Simplified
                (Maze)      Representation
   Three types of detailed routing methods:
    •   Channel Routing
    •   2-D Switchbox Routing
    •   3-D Switchbox Routing
   Channel routing → 2-D switchbox → 3-D switchbox
   If the switchbox or channels are unroutable without a large
    expansion, global routing needs to be done again.
o   Channel routing:
    o   channel may grow in one dimension to accommodate wires;
    o   pins generally on only two opposite sides.
o   Switchbox routing:
    o   Switch box routing is harder than channel routing because we
        can’t expand the switchbox to make room for more wires.
    o   pins are on all four sides, fixing dimensions of the box.
channel   switchbox   switchbox
                      pins




           channel
Three types of channel junctions may occur:
o   L-type: Occurs at the corners of the layout surface. Can be
    routed using channel routers.
o   T-type: The leg of the “T” must be routed before the shoulder.
    Can be routed using channel routers.
o   +-type: More complex and requires switchbox routers.
    Advantageous to convert +-junctions to T-junctions.
   Channel routing is a special case of the routing problem in
    which wires are connected within the routing channels.
   To apply channel routing, a routing region is usually
    decomposed into routing channels.
a)     Channels have no conflicts
b)     Conflicting channels
c)     Conflict resolved using L-shaped channels
     •   Order matters
d)     Switchbox used to resolve the conflict
     •   Order matters
     •   Harder problem (compared to channel routing)
   After global routing and detailed routing, information of the
    nets can be extracted and delays can be analyzed.
   If some nets fail to meet their timing budget, detailed routing
    and/or global routing needs to be repeated.
 NTHU – Route
 MaizeRouter

 BoxRouter

 Archer

 FastRoute

 NTUgr

 FASHION
   Routing is one of the most fundamental steps in the physical
    design flow and is typically a very complex optimization
    problem.
   Effective and efficient routing algorithms are essential to handle
    the challenges arising from the fast growing scaling of IC
    integration.
   We have discussed Global and Detailed routing techniques.
   Routers will keep evolving with emerging design challenges such
    as nanometer effects, signal integrity, reliability etc.
                      33
   “Global and detailed routing”, Huang-Yu Chen and Yao-Wen Chang,
    National Taiwan University, Taipei, Taiwan,
   “VLSI Layout synthesis”, Local search in Combinatorial Optimization,
    Emile H.L. Aarts, Philips Research Laboratories, Eindhoven.
   Michael D. Moffitt, IBM Research “Global routing revisited”. Computer-
    Aided Design - Digest of Technical Papers, 2009. ICCAD 2009.
    IEEE/ACM International Conference , Pages: 805 - 808
35

Contenu connexe

Tendances

Physical design-complete
Physical design-completePhysical design-complete
Physical design-completeMurali Rai
 
Low power vlsi design ppt
Low power vlsi design pptLow power vlsi design ppt
Low power vlsi design pptAnil Yadav
 
Placement and algorithm.
Placement and algorithm.Placement and algorithm.
Placement and algorithm.Ashish Singh
 
VLSI circuit design process
VLSI circuit design processVLSI circuit design process
VLSI circuit design processVishal kakade
 
Physical Verification Design.pdf
Physical Verification Design.pdfPhysical Verification Design.pdf
Physical Verification Design.pdfAhmed Abdelazeem
 
Placement and routing in full custom physical design
Placement and routing in full custom physical designPlacement and routing in full custom physical design
Placement and routing in full custom physical designDeiptii Das
 
Define Width and Height of Core and Die (http://www.vlsisystemdesign.com/PD-F...
Define Width and Height of Core and Die (http://www.vlsisystemdesign.com/PD-F...Define Width and Height of Core and Die (http://www.vlsisystemdesign.com/PD-F...
Define Width and Height of Core and Die (http://www.vlsisystemdesign.com/PD-F...VLSI SYSTEM Design
 
Multi mode multi corner (mmmc)
Multi mode multi corner (mmmc)Multi mode multi corner (mmmc)
Multi mode multi corner (mmmc)shaik sharief
 
fpga programming
fpga programmingfpga programming
fpga programmingAnish Gupta
 
Coherent and Non-coherent detection of ASK, FSK AND QASK
Coherent and Non-coherent detection of ASK, FSK AND QASKCoherent and Non-coherent detection of ASK, FSK AND QASK
Coherent and Non-coherent detection of ASK, FSK AND QASKnaimish12
 
Dft (design for testability)
Dft (design for testability)Dft (design for testability)
Dft (design for testability)shaik sharief
 
Vlsi physical design-notes
Vlsi physical design-notesVlsi physical design-notes
Vlsi physical design-notesDr.YNM
 

Tendances (20)

Vlsi design flow
Vlsi design flowVlsi design flow
Vlsi design flow
 
Physical design-complete
Physical design-completePhysical design-complete
Physical design-complete
 
ASIC DESIGN FLOW
ASIC DESIGN FLOWASIC DESIGN FLOW
ASIC DESIGN FLOW
 
Asic design flow
Asic design flowAsic design flow
Asic design flow
 
Actel fpga
Actel fpgaActel fpga
Actel fpga
 
Low power vlsi design ppt
Low power vlsi design pptLow power vlsi design ppt
Low power vlsi design ppt
 
Placement and algorithm.
Placement and algorithm.Placement and algorithm.
Placement and algorithm.
 
Vlsi design notes
Vlsi design notesVlsi design notes
Vlsi design notes
 
VLSI circuit design process
VLSI circuit design processVLSI circuit design process
VLSI circuit design process
 
Physical Verification Design.pdf
Physical Verification Design.pdfPhysical Verification Design.pdf
Physical Verification Design.pdf
 
Placement and routing in full custom physical design
Placement and routing in full custom physical designPlacement and routing in full custom physical design
Placement and routing in full custom physical design
 
Define Width and Height of Core and Die (http://www.vlsisystemdesign.com/PD-F...
Define Width and Height of Core and Die (http://www.vlsisystemdesign.com/PD-F...Define Width and Height of Core and Die (http://www.vlsisystemdesign.com/PD-F...
Define Width and Height of Core and Die (http://www.vlsisystemdesign.com/PD-F...
 
Floor plan & Power Plan
Floor plan & Power Plan Floor plan & Power Plan
Floor plan & Power Plan
 
Multi mode multi corner (mmmc)
Multi mode multi corner (mmmc)Multi mode multi corner (mmmc)
Multi mode multi corner (mmmc)
 
fpga programming
fpga programmingfpga programming
fpga programming
 
Coherent and Non-coherent detection of ASK, FSK AND QASK
Coherent and Non-coherent detection of ASK, FSK AND QASKCoherent and Non-coherent detection of ASK, FSK AND QASK
Coherent and Non-coherent detection of ASK, FSK AND QASK
 
Dft (design for testability)
Dft (design for testability)Dft (design for testability)
Dft (design for testability)
 
Vlsi physical design-notes
Vlsi physical design-notesVlsi physical design-notes
Vlsi physical design-notes
 
Equalization
EqualizationEqualization
Equalization
 
Introduction to FPGAs
Introduction to FPGAsIntroduction to FPGAs
Introduction to FPGAs
 

Similaire à VLSI routing

COMPUTER NETWORKS CHAPTER 3 NETWORK LAYER NOTES CSE 3RD year sem 1
COMPUTER NETWORKS CHAPTER 3 NETWORK LAYER NOTES CSE 3RD year sem 1COMPUTER NETWORKS CHAPTER 3 NETWORK LAYER NOTES CSE 3RD year sem 1
COMPUTER NETWORKS CHAPTER 3 NETWORK LAYER NOTES CSE 3RD year sem 1aishwaryaarrao3
 
Physical organization of parallel platforms
Physical organization of parallel platformsPhysical organization of parallel platforms
Physical organization of parallel platformsSyed Zaid Irshad
 
minimisation of crosstalk in VLSI routing
minimisation of crosstalk in VLSI routingminimisation of crosstalk in VLSI routing
minimisation of crosstalk in VLSI routingChandrajit Pal
 
crosstalk minimisation using vlsi
crosstalk minimisation using vlsicrosstalk minimisation using vlsi
crosstalk minimisation using vlsisubhradeep mitra
 
Lecture24 clockpower routing
Lecture24 clockpower routingLecture24 clockpower routing
Lecture24 clockpower routingfreeloadtailieu
 
L22.ppt
L22.pptL22.ppt
L22.pptraaed5
 
24-ad-hoc.ppt
24-ad-hoc.ppt24-ad-hoc.ppt
24-ad-hoc.pptsumadi26
 
Routing Presentation
Routing PresentationRouting Presentation
Routing PresentationMohsin Ali
 
Radio Resource Management for Millimeter Wave & Massive MIMO
Radio Resource Management for Millimeter Wave & Massive MIMORadio Resource Management for Millimeter Wave & Massive MIMO
Radio Resource Management for Millimeter Wave & Massive MIMOEduardo Castañeda
 
Parallel computing chapter 2
Parallel computing chapter 2Parallel computing chapter 2
Parallel computing chapter 2Md. Mahedi Mahfuj
 
system interconnect architectures in ACA
system interconnect architectures in ACAsystem interconnect architectures in ACA
system interconnect architectures in ACAPankaj Kumar Jain
 
Introduction to mobile ad hoc network (m.a.net)
Introduction to mobile ad hoc network (m.a.net)Introduction to mobile ad hoc network (m.a.net)
Introduction to mobile ad hoc network (m.a.net)Sohebuzzaman Khan
 

Similaire à VLSI routing (20)

Routing.ppt
Routing.pptRouting.ppt
Routing.ppt
 
COMPUTER NETWORKS CHAPTER 3 NETWORK LAYER NOTES CSE 3RD year sem 1
COMPUTER NETWORKS CHAPTER 3 NETWORK LAYER NOTES CSE 3RD year sem 1COMPUTER NETWORKS CHAPTER 3 NETWORK LAYER NOTES CSE 3RD year sem 1
COMPUTER NETWORKS CHAPTER 3 NETWORK LAYER NOTES CSE 3RD year sem 1
 
Physical organization of parallel platforms
Physical organization of parallel platformsPhysical organization of parallel platforms
Physical organization of parallel platforms
 
minimisation of crosstalk in VLSI routing
minimisation of crosstalk in VLSI routingminimisation of crosstalk in VLSI routing
minimisation of crosstalk in VLSI routing
 
Floor planning ppt
Floor planning pptFloor planning ppt
Floor planning ppt
 
Channel routing
Channel routingChannel routing
Channel routing
 
crosstalk minimisation using vlsi
crosstalk minimisation using vlsicrosstalk minimisation using vlsi
crosstalk minimisation using vlsi
 
Lecture24 clockpower routing
Lecture24 clockpower routingLecture24 clockpower routing
Lecture24 clockpower routing
 
Network layer
Network layerNetwork layer
Network layer
 
Network
NetworkNetwork
Network
 
L22.ppt
L22.pptL22.ppt
L22.ppt
 
Synchronous optical networking (SONET)
Synchronous optical networking (SONET) Synchronous optical networking (SONET)
Synchronous optical networking (SONET)
 
24-ad-hoc.ppt
24-ad-hoc.ppt24-ad-hoc.ppt
24-ad-hoc.ppt
 
Routing Presentation
Routing PresentationRouting Presentation
Routing Presentation
 
Taiwan course
Taiwan courseTaiwan course
Taiwan course
 
Radio Resource Management for Millimeter Wave & Massive MIMO
Radio Resource Management for Millimeter Wave & Massive MIMORadio Resource Management for Millimeter Wave & Massive MIMO
Radio Resource Management for Millimeter Wave & Massive MIMO
 
Parallel computing chapter 2
Parallel computing chapter 2Parallel computing chapter 2
Parallel computing chapter 2
 
system interconnect architectures in ACA
system interconnect architectures in ACAsystem interconnect architectures in ACA
system interconnect architectures in ACA
 
Introduction to mobile ad hoc network (m.a.net)
Introduction to mobile ad hoc network (m.a.net)Introduction to mobile ad hoc network (m.a.net)
Introduction to mobile ad hoc network (m.a.net)
 
09 placement
09 placement09 placement
09 placement
 

Plus de Naveen Kumar

Security in GSM(2G) and UMTS(3G) Networks
Security in GSM(2G) and UMTS(3G) NetworksSecurity in GSM(2G) and UMTS(3G) Networks
Security in GSM(2G) and UMTS(3G) NetworksNaveen Kumar
 
Mobile tower radiation
Mobile tower radiationMobile tower radiation
Mobile tower radiationNaveen Kumar
 
Ph.D Research proposal
Ph.D Research proposalPh.D Research proposal
Ph.D Research proposalNaveen Kumar
 
Cell Phone Antennas
Cell Phone AntennasCell Phone Antennas
Cell Phone AntennasNaveen Kumar
 
VHDL coding in Xilinx
VHDL coding in XilinxVHDL coding in Xilinx
VHDL coding in XilinxNaveen Kumar
 
Optimization in HFSS
Optimization in HFSSOptimization in HFSS
Optimization in HFSSNaveen Kumar
 
Free space optical communication
Free space optical communicationFree space optical communication
Free space optical communicationNaveen Kumar
 
A Multi-Band PIFA with Slotted Ground Plane
A Multi-Band PIFA with Slotted Ground Plane A Multi-Band PIFA with Slotted Ground Plane
A Multi-Band PIFA with Slotted Ground Plane Naveen Kumar
 
Study of Planar Inverted - F Antenna (PIFA) for mobile devices
Study of Planar Inverted - F Antenna (PIFA) for mobile devices Study of Planar Inverted - F Antenna (PIFA) for mobile devices
Study of Planar Inverted - F Antenna (PIFA) for mobile devices Naveen Kumar
 
A novel low profile planar inverted f antenna (pifa) for mobile handsets
A novel low profile planar inverted f antenna (pifa) for mobile handsetsA novel low profile planar inverted f antenna (pifa) for mobile handsets
A novel low profile planar inverted f antenna (pifa) for mobile handsetsNaveen Kumar
 
A compact planar inverted-F antenna with slotted ground plane
A compact planar inverted-F antenna with slotted ground planeA compact planar inverted-F antenna with slotted ground plane
A compact planar inverted-F antenna with slotted ground planeNaveen Kumar
 
Secure Socket Layer
Secure Socket LayerSecure Socket Layer
Secure Socket LayerNaveen Kumar
 
Adaptive Resonance Theory
Adaptive Resonance TheoryAdaptive Resonance Theory
Adaptive Resonance TheoryNaveen Kumar
 
HDLC, PPP and SLIP
HDLC, PPP and SLIPHDLC, PPP and SLIP
HDLC, PPP and SLIPNaveen Kumar
 

Plus de Naveen Kumar (20)

Security in GSM(2G) and UMTS(3G) Networks
Security in GSM(2G) and UMTS(3G) NetworksSecurity in GSM(2G) and UMTS(3G) Networks
Security in GSM(2G) and UMTS(3G) Networks
 
Mobile tower radiation
Mobile tower radiationMobile tower radiation
Mobile tower radiation
 
Mobile security
Mobile securityMobile security
Mobile security
 
Ph.D Research proposal
Ph.D Research proposalPh.D Research proposal
Ph.D Research proposal
 
Wi-Fi Technology
Wi-Fi TechnologyWi-Fi Technology
Wi-Fi Technology
 
Cell Phone Antennas
Cell Phone AntennasCell Phone Antennas
Cell Phone Antennas
 
Thesis on PIFA
Thesis on PIFAThesis on PIFA
Thesis on PIFA
 
Electronics Quiz
Electronics QuizElectronics Quiz
Electronics Quiz
 
VHDL coding in Xilinx
VHDL coding in XilinxVHDL coding in Xilinx
VHDL coding in Xilinx
 
Optimization in HFSS
Optimization in HFSSOptimization in HFSS
Optimization in HFSS
 
Free space optical communication
Free space optical communicationFree space optical communication
Free space optical communication
 
A Multi-Band PIFA with Slotted Ground Plane
A Multi-Band PIFA with Slotted Ground Plane A Multi-Band PIFA with Slotted Ground Plane
A Multi-Band PIFA with Slotted Ground Plane
 
Study of Planar Inverted - F Antenna (PIFA) for mobile devices
Study of Planar Inverted - F Antenna (PIFA) for mobile devices Study of Planar Inverted - F Antenna (PIFA) for mobile devices
Study of Planar Inverted - F Antenna (PIFA) for mobile devices
 
A novel low profile planar inverted f antenna (pifa) for mobile handsets
A novel low profile planar inverted f antenna (pifa) for mobile handsetsA novel low profile planar inverted f antenna (pifa) for mobile handsets
A novel low profile planar inverted f antenna (pifa) for mobile handsets
 
A compact planar inverted-F antenna with slotted ground plane
A compact planar inverted-F antenna with slotted ground planeA compact planar inverted-F antenna with slotted ground plane
A compact planar inverted-F antenna with slotted ground plane
 
Secure Socket Layer
Secure Socket LayerSecure Socket Layer
Secure Socket Layer
 
Adaptive Resonance Theory
Adaptive Resonance TheoryAdaptive Resonance Theory
Adaptive Resonance Theory
 
UART
UARTUART
UART
 
HDLC, PPP and SLIP
HDLC, PPP and SLIPHDLC, PPP and SLIP
HDLC, PPP and SLIP
 
AR model
AR modelAR model
AR model
 

Dernier

EMPOWERMENT TECHNOLOGY GRADE 11 QUARTER 2 REVIEWER
EMPOWERMENT TECHNOLOGY GRADE 11 QUARTER 2 REVIEWEREMPOWERMENT TECHNOLOGY GRADE 11 QUARTER 2 REVIEWER
EMPOWERMENT TECHNOLOGY GRADE 11 QUARTER 2 REVIEWERMadyBayot
 
Boost Fertility New Invention Ups Success Rates.pdf
Boost Fertility New Invention Ups Success Rates.pdfBoost Fertility New Invention Ups Success Rates.pdf
Boost Fertility New Invention Ups Success Rates.pdfsudhanshuwaghmare1
 
Modular Monolith - a Practical Alternative to Microservices @ Devoxx UK 2024
Modular Monolith - a Practical Alternative to Microservices @ Devoxx UK 2024Modular Monolith - a Practical Alternative to Microservices @ Devoxx UK 2024
Modular Monolith - a Practical Alternative to Microservices @ Devoxx UK 2024Victor Rentea
 
Artificial Intelligence Chap.5 : Uncertainty
Artificial Intelligence Chap.5 : UncertaintyArtificial Intelligence Chap.5 : Uncertainty
Artificial Intelligence Chap.5 : UncertaintyKhushali Kathiriya
 
Biography Of Angeliki Cooney | Senior Vice President Life Sciences | Albany, ...
Biography Of Angeliki Cooney | Senior Vice President Life Sciences | Albany, ...Biography Of Angeliki Cooney | Senior Vice President Life Sciences | Albany, ...
Biography Of Angeliki Cooney | Senior Vice President Life Sciences | Albany, ...Angeliki Cooney
 
Apidays New York 2024 - Scaling API-first by Ian Reasor and Radu Cotescu, Adobe
Apidays New York 2024 - Scaling API-first by Ian Reasor and Radu Cotescu, AdobeApidays New York 2024 - Scaling API-first by Ian Reasor and Radu Cotescu, Adobe
Apidays New York 2024 - Scaling API-first by Ian Reasor and Radu Cotescu, Adobeapidays
 
WSO2's API Vision: Unifying Control, Empowering Developers
WSO2's API Vision: Unifying Control, Empowering DevelopersWSO2's API Vision: Unifying Control, Empowering Developers
WSO2's API Vision: Unifying Control, Empowering DevelopersWSO2
 
Architecting Cloud Native Applications
Architecting Cloud Native ApplicationsArchitecting Cloud Native Applications
Architecting Cloud Native ApplicationsWSO2
 
Six Myths about Ontologies: The Basics of Formal Ontology
Six Myths about Ontologies: The Basics of Formal OntologySix Myths about Ontologies: The Basics of Formal Ontology
Six Myths about Ontologies: The Basics of Formal Ontologyjohnbeverley2021
 
[BuildWithAI] Introduction to Gemini.pdf
[BuildWithAI] Introduction to Gemini.pdf[BuildWithAI] Introduction to Gemini.pdf
[BuildWithAI] Introduction to Gemini.pdfSandro Moreira
 
AWS Community Day CPH - Three problems of Terraform
AWS Community Day CPH - Three problems of TerraformAWS Community Day CPH - Three problems of Terraform
AWS Community Day CPH - Three problems of TerraformAndrey Devyatkin
 
DBX First Quarter 2024 Investor Presentation
DBX First Quarter 2024 Investor PresentationDBX First Quarter 2024 Investor Presentation
DBX First Quarter 2024 Investor PresentationDropbox
 
Strategies for Landing an Oracle DBA Job as a Fresher
Strategies for Landing an Oracle DBA Job as a FresherStrategies for Landing an Oracle DBA Job as a Fresher
Strategies for Landing an Oracle DBA Job as a FresherRemote DBA Services
 
ProductAnonymous-April2024-WinProductDiscovery-MelissaKlemke
ProductAnonymous-April2024-WinProductDiscovery-MelissaKlemkeProductAnonymous-April2024-WinProductDiscovery-MelissaKlemke
ProductAnonymous-April2024-WinProductDiscovery-MelissaKlemkeProduct Anonymous
 
Finding Java's Hidden Performance Traps @ DevoxxUK 2024
Finding Java's Hidden Performance Traps @ DevoxxUK 2024Finding Java's Hidden Performance Traps @ DevoxxUK 2024
Finding Java's Hidden Performance Traps @ DevoxxUK 2024Victor Rentea
 
Why Teams call analytics are critical to your entire business
Why Teams call analytics are critical to your entire businessWhy Teams call analytics are critical to your entire business
Why Teams call analytics are critical to your entire businesspanagenda
 
Corporate and higher education May webinar.pptx
Corporate and higher education May webinar.pptxCorporate and higher education May webinar.pptx
Corporate and higher education May webinar.pptxRustici Software
 
Apidays New York 2024 - Accelerating FinTech Innovation by Vasa Krishnan, Fin...
Apidays New York 2024 - Accelerating FinTech Innovation by Vasa Krishnan, Fin...Apidays New York 2024 - Accelerating FinTech Innovation by Vasa Krishnan, Fin...
Apidays New York 2024 - Accelerating FinTech Innovation by Vasa Krishnan, Fin...apidays
 
"I see eyes in my soup": How Delivery Hero implemented the safety system for ...
"I see eyes in my soup": How Delivery Hero implemented the safety system for ..."I see eyes in my soup": How Delivery Hero implemented the safety system for ...
"I see eyes in my soup": How Delivery Hero implemented the safety system for ...Zilliz
 

Dernier (20)

EMPOWERMENT TECHNOLOGY GRADE 11 QUARTER 2 REVIEWER
EMPOWERMENT TECHNOLOGY GRADE 11 QUARTER 2 REVIEWEREMPOWERMENT TECHNOLOGY GRADE 11 QUARTER 2 REVIEWER
EMPOWERMENT TECHNOLOGY GRADE 11 QUARTER 2 REVIEWER
 
Boost Fertility New Invention Ups Success Rates.pdf
Boost Fertility New Invention Ups Success Rates.pdfBoost Fertility New Invention Ups Success Rates.pdf
Boost Fertility New Invention Ups Success Rates.pdf
 
Modular Monolith - a Practical Alternative to Microservices @ Devoxx UK 2024
Modular Monolith - a Practical Alternative to Microservices @ Devoxx UK 2024Modular Monolith - a Practical Alternative to Microservices @ Devoxx UK 2024
Modular Monolith - a Practical Alternative to Microservices @ Devoxx UK 2024
 
Artificial Intelligence Chap.5 : Uncertainty
Artificial Intelligence Chap.5 : UncertaintyArtificial Intelligence Chap.5 : Uncertainty
Artificial Intelligence Chap.5 : Uncertainty
 
Biography Of Angeliki Cooney | Senior Vice President Life Sciences | Albany, ...
Biography Of Angeliki Cooney | Senior Vice President Life Sciences | Albany, ...Biography Of Angeliki Cooney | Senior Vice President Life Sciences | Albany, ...
Biography Of Angeliki Cooney | Senior Vice President Life Sciences | Albany, ...
 
Apidays New York 2024 - Scaling API-first by Ian Reasor and Radu Cotescu, Adobe
Apidays New York 2024 - Scaling API-first by Ian Reasor and Radu Cotescu, AdobeApidays New York 2024 - Scaling API-first by Ian Reasor and Radu Cotescu, Adobe
Apidays New York 2024 - Scaling API-first by Ian Reasor and Radu Cotescu, Adobe
 
WSO2's API Vision: Unifying Control, Empowering Developers
WSO2's API Vision: Unifying Control, Empowering DevelopersWSO2's API Vision: Unifying Control, Empowering Developers
WSO2's API Vision: Unifying Control, Empowering Developers
 
Architecting Cloud Native Applications
Architecting Cloud Native ApplicationsArchitecting Cloud Native Applications
Architecting Cloud Native Applications
 
Six Myths about Ontologies: The Basics of Formal Ontology
Six Myths about Ontologies: The Basics of Formal OntologySix Myths about Ontologies: The Basics of Formal Ontology
Six Myths about Ontologies: The Basics of Formal Ontology
 
[BuildWithAI] Introduction to Gemini.pdf
[BuildWithAI] Introduction to Gemini.pdf[BuildWithAI] Introduction to Gemini.pdf
[BuildWithAI] Introduction to Gemini.pdf
 
AWS Community Day CPH - Three problems of Terraform
AWS Community Day CPH - Three problems of TerraformAWS Community Day CPH - Three problems of Terraform
AWS Community Day CPH - Three problems of Terraform
 
DBX First Quarter 2024 Investor Presentation
DBX First Quarter 2024 Investor PresentationDBX First Quarter 2024 Investor Presentation
DBX First Quarter 2024 Investor Presentation
 
Strategies for Landing an Oracle DBA Job as a Fresher
Strategies for Landing an Oracle DBA Job as a FresherStrategies for Landing an Oracle DBA Job as a Fresher
Strategies for Landing an Oracle DBA Job as a Fresher
 
ProductAnonymous-April2024-WinProductDiscovery-MelissaKlemke
ProductAnonymous-April2024-WinProductDiscovery-MelissaKlemkeProductAnonymous-April2024-WinProductDiscovery-MelissaKlemke
ProductAnonymous-April2024-WinProductDiscovery-MelissaKlemke
 
Finding Java's Hidden Performance Traps @ DevoxxUK 2024
Finding Java's Hidden Performance Traps @ DevoxxUK 2024Finding Java's Hidden Performance Traps @ DevoxxUK 2024
Finding Java's Hidden Performance Traps @ DevoxxUK 2024
 
Why Teams call analytics are critical to your entire business
Why Teams call analytics are critical to your entire businessWhy Teams call analytics are critical to your entire business
Why Teams call analytics are critical to your entire business
 
Corporate and higher education May webinar.pptx
Corporate and higher education May webinar.pptxCorporate and higher education May webinar.pptx
Corporate and higher education May webinar.pptx
 
Apidays New York 2024 - Accelerating FinTech Innovation by Vasa Krishnan, Fin...
Apidays New York 2024 - Accelerating FinTech Innovation by Vasa Krishnan, Fin...Apidays New York 2024 - Accelerating FinTech Innovation by Vasa Krishnan, Fin...
Apidays New York 2024 - Accelerating FinTech Innovation by Vasa Krishnan, Fin...
 
Understanding the FAA Part 107 License ..
Understanding the FAA Part 107 License ..Understanding the FAA Part 107 License ..
Understanding the FAA Part 107 License ..
 
"I see eyes in my soup": How Delivery Hero implemented the safety system for ...
"I see eyes in my soup": How Delivery Hero implemented the safety system for ..."I see eyes in my soup": How Delivery Hero implemented the safety system for ...
"I see eyes in my soup": How Delivery Hero implemented the safety system for ...
 

VLSI routing

  • 1.
  • 2. Routing  Routing Problem  Routing Regions  Types of Routing -Global Routing -Detailed Routing  Conclusion  References
  • 3. o The routing is to locate a set of wires in the routing space that connect all the nets in the net list. The capacities of channels, width of wires, and wire crossings often need to be taken into consideration .
  • 4. Apply after placement  Input:  Netlist  Timing budget for, typically, critical nets  Locations of blocks and locations of pins  Output:  Geometric layouts of all nets  Objective:  Minimize the total wire length, the number of vias, or just completing all connections without increasing the chip area.  Each net meets its timing budget.
  • 5. For a multi-terminal net, we can construct a spanning tree to connect all the terminals together.  But the wire length will be large.  Better use Steiner Tree: Steiner A tree connecting all terminals and some Node additional nodes (Steiner nodes).  Rectilinear Steiner Tree: Steiner tree in which all the edges run horizontally and vertically.
  • 6. Minimum Steiner Tree Problem:  Given a net, find the steiner tree with the minimum length.  This problem is NP-Complete!  May need to route tens of thousands of nets simultaneously without overlapping.  Obstacles may exist in the routing region.
  • 8. Divide the routing area into routing regions of simple shape (rectangular): Switchbox Channel • Channel: Pins on 2 opposite sides. • 2-D Switchbox: Pins on 4 sides. • 3-D Switchbox: Pins on all 6 sides.
  • 9.
  • 10. Gate-Array Standard-Cell Full-Custom Feedthrough Cell
  • 11. Routing Detailed Global routing routing Channel Switch Box Line Routing Maze Routing Routing Routing
  • 12. Placement Global routing Generate a 'loose' route for each net Assign a list of routing region to each net without specifying the actual layout of wires. Detailed routing Find the actual geometry layout of each net with in the assigned routing regions Compaction
  • 13.
  • 14. o Minimize the total overflow o Minimize the total wire length o Minimize running time
  • 15. Assign routing regions to each net. Need to consider timing budget of nets and routing congestion of the regions.
  • 16. Assign pins on routing region boundaries for each net. (Prepare for the detailed routing stage for each region.)
  • 17. Sequential Approach:  Route the nets one at a time.  Order dependent on factors like criticality, estimated wire length, etc.  If further routing is impossible because some nets are blocked by nets routed earlier, apply Rip-up and Reroute technique.  This approach is much more popular.
  • 18. Concurrent Approach:  The major drawback of the sequential approach is that it suffers from the net ordering problem.  Consider all nets simultaneously.  Can be formulated as an integer program.
  • 19.
  • 20. Given:  A planar rectangular grid graph.  Two points S and T on the graph.  Obstacles modeled as blocked vertices.  Objective:  Find the shortest path connecting S and T.  This technique can be used in global or detailed routing (switchbox) problems.
  • 21. S S S  T X X  T X X  T Area Routing Grid Graph Simplified (Maze) Representation
  • 22.
  • 23.
  • 24. Three types of detailed routing methods: • Channel Routing • 2-D Switchbox Routing • 3-D Switchbox Routing  Channel routing → 2-D switchbox → 3-D switchbox  If the switchbox or channels are unroutable without a large expansion, global routing needs to be done again.
  • 25. o Channel routing: o channel may grow in one dimension to accommodate wires; o pins generally on only two opposite sides. o Switchbox routing: o Switch box routing is harder than channel routing because we can’t expand the switchbox to make room for more wires. o pins are on all four sides, fixing dimensions of the box.
  • 26. channel switchbox switchbox pins channel
  • 27. Three types of channel junctions may occur: o L-type: Occurs at the corners of the layout surface. Can be routed using channel routers. o T-type: The leg of the “T” must be routed before the shoulder. Can be routed using channel routers. o +-type: More complex and requires switchbox routers. Advantageous to convert +-junctions to T-junctions.
  • 28.
  • 29. Channel routing is a special case of the routing problem in which wires are connected within the routing channels.  To apply channel routing, a routing region is usually decomposed into routing channels.
  • 30. a) Channels have no conflicts b) Conflicting channels c) Conflict resolved using L-shaped channels • Order matters d) Switchbox used to resolve the conflict • Order matters • Harder problem (compared to channel routing)
  • 31. After global routing and detailed routing, information of the nets can be extracted and delays can be analyzed.  If some nets fail to meet their timing budget, detailed routing and/or global routing needs to be repeated.
  • 32.  NTHU – Route  MaizeRouter  BoxRouter  Archer  FastRoute  NTUgr  FASHION
  • 33. Routing is one of the most fundamental steps in the physical design flow and is typically a very complex optimization problem.  Effective and efficient routing algorithms are essential to handle the challenges arising from the fast growing scaling of IC integration.  We have discussed Global and Detailed routing techniques.  Routers will keep evolving with emerging design challenges such as nanometer effects, signal integrity, reliability etc. 33
  • 34. “Global and detailed routing”, Huang-Yu Chen and Yao-Wen Chang, National Taiwan University, Taipei, Taiwan,  “VLSI Layout synthesis”, Local search in Combinatorial Optimization, Emile H.L. Aarts, Philips Research Laboratories, Eindhoven.  Michael D. Moffitt, IBM Research “Global routing revisited”. Computer- Aided Design - Digest of Technical Papers, 2009. ICCAD 2009. IEEE/ACM International Conference , Pages: 805 - 808
  • 35. 35