Personal Information
Entreprise/Lieu de travail
Gurgaon, India India
Secteur d’activité
Education
Site Web
www.teamvlsiitmu.wordpress.com
À propos
Academic researcher in VLSI domail
Mots-clés
team-vlsi
rajesh yadav
cad
computer aided vlsi design
itm-university
backend design
floorplanning
vlsi
computer aided design
itm university
linux
vlsi design
partitioning
routing
backend
synopsys tcad
verification
randomization
systemverilog
ra
embedded system design. esd
if
intermediate fabrics
embedded syastem design
rtx kernal
esd
future material
cntfet
neural network
carbon nano tube
cnt
nano technology
open source
scripting
paython
placement in vlsi design
robdd
bdd
reduced ordered binary decision diagram
threshold voltage
nmos
rehat
unix
linux cammand
layout extraction
layout
layout compaction
global routing
cmos inverter
180nm technology
ledit
tanner
7t sram
6t sram
low power
sram
ultra low voltage operation
gain bandwidth product
delay
bandwidth
frequency
dynamic power
average power
design
static power
transconductance
small signal analysis of mosfet
output resistance
mosfet
high frequency equivelence
low frequency equivelence
fabrication
twin well
cmos
Tout plus
Présentations
(17)Documents
(3)J’aime
(1)Cadence P-cell tutorial
Michael Lee
•
il y a 10 ans
Personal Information
Entreprise/Lieu de travail
Gurgaon, India India
Secteur d’activité
Education
Site Web
www.teamvlsiitmu.wordpress.com
À propos
Academic researcher in VLSI domail
Mots-clés
team-vlsi
rajesh yadav
cad
computer aided vlsi design
itm-university
backend design
floorplanning
vlsi
computer aided design
itm university
linux
vlsi design
partitioning
routing
backend
synopsys tcad
verification
randomization
systemverilog
ra
embedded system design. esd
if
intermediate fabrics
embedded syastem design
rtx kernal
esd
future material
cntfet
neural network
carbon nano tube
cnt
nano technology
open source
scripting
paython
placement in vlsi design
robdd
bdd
reduced ordered binary decision diagram
threshold voltage
nmos
rehat
unix
linux cammand
layout extraction
layout
layout compaction
global routing
cmos inverter
180nm technology
ledit
tanner
7t sram
6t sram
low power
sram
ultra low voltage operation
gain bandwidth product
delay
bandwidth
frequency
dynamic power
average power
design
static power
transconductance
small signal analysis of mosfet
output resistance
mosfet
high frequency equivelence
low frequency equivelence
fabrication
twin well
cmos
Tout plus