2. Lecture 5:
Logic Gates and Circuits
Logic Gates
The Inverter
The AND Gate
The OR Gate
The NAND Gate
The NOR Gate
The XOR Gate
The XNOR Gate
Drawing Logic Circuit
Analysing Logic Circuit
Propagation Delay
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Logic Gates
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3. Lecture 4:
Logic Gates and Circuits
Universal Gates: NAND and NOR
NAND Gate
NOR Gate
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Implementation using NAND Gates
Implementation using NOR Gates
Implementation of SOP Expressions
Implementation of POS Expressions
Positive and Negative Logic
Integrated Circuit Logic Families
Logic Gates
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4. Logic Gates
Gate Symbols
AND
OR
NOT
a
b
a
b
a
a
NAND
NOR
EXCLUSIVE OR
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Symbol set 2
Symbol set 1
b
a
b
a
b
Logic Gates
a.b
a+b
a'
(a.b)'
(a+b)'
a⊕ b
(ANSI/IEEE Standard 91-1984)
a
&
a.b
b
a
b
a
a
b
a
b
a
b
≥1
a+b
1
a'
&
(a.b)'
≥1
(a+b)'
=1
a⊕b
4
5. Logic Gates: The Inverter
The Inverter
A A'
A
A'
A
0
1
A'
1
0
Application of the inverter: complement.
1
1
Binary number
0
1
0
0
0
0
1
0
1
1
0
1
1
0
1’s Complement
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Logic Gates
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6. Logic Gates: The AND Gate
The AND Gate
A
A.B
B
A
0
0
1
1
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B
0
1
0
1
A
B
&
A.B
A.B
0
0
0
1
Logic Gates
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7. Logic Gates: The AND Gate
Application of the AND Gate
1 sec
A
A
Enable
Counter
Enable
1 sec
Reset to zero
between
Enable pulses
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Logic Gates
Register,
decode
and
frequency
display
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8. Logic Gates: The OR Gate
The OR Gate
A
A+B
B
A
0
0
1
1
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B
0
1
0
1
A
B
≥
1
A+B
A+B
0
1
1
1
Logic Gates
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9. Logic Gates: The NAND Gate
The NAND Gate
A
(A.B)'
B
A
0
0
1
1
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B
0
1
0
1
≡
A
(A.B)'
B
(A.B)'
1
1
1
0
A
B
&
(A.B)'
≡
NAND
Logic Gates
Negative-OR
9
10. Logic Gates: The NOR Gate
The NOR Gate
A
(A+B)'
B
A
0
0
1
1
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B
0
1
0
1
≡
A
(A+B)'
B
(A+B)'
1
0
0
0
A
B
≥
1
(A+B)'
≡
NOR
Logic Gates
Negative-AND
10
11. Logic Gates: The XOR Gate
The XOR Gate
A
A⊕B
B
A
0
0
1
1
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B
0
1
0
1
A
B
=1
A⊕B
A ⊕B
0
1
1
0
Logic Gates
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12. Logic Gates: The XNOR Gate
The XNOR Gate
A
(A ⊕ B)'
B
A
0
0
1
1
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A
B
=1
(A ⊕ B)'
B (A ⊕ B) '
0
1
1
0
0
0
1
1
Logic Gates
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13. Drawing Logic Circuit
When a Boolean expression is provided, we can easily
draw the logic circuit.
Examples:
(i) F1 = xyz' (note the use of a 3-input AND gate)
x
y
z
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F1
z'
Logic Gates
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14. Drawing Logic Circuit
(ii) F2 = x + y'z (can assume that variables and their
complements are available)
x
F2
y'
z
(iii) F3 = xy' + x'z
y'z
x
y'
xy'
F3
x'
z
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Logic Gates
x'z
14
15. Analysing Logic Circuit
When a logic circuit is provided, we can analyse the circuit
to obtain the logic expression.
Example: What is the Boolean expression of F4?
A'
A'B'
B'
A'B'+C
C
(A'B'+C)'
F4
F4 = (A'B'+C)' = (A+B).C'
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Logic Gates
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16. Propagation Delay
Every logic gate experiences some delay (though very
small) in propagating signals forward.
This delay is called Gate (Propagation) Delay.
Delay
Formally, it is the average transition time taken for the
output signal of the gate to change in response to changes
in the input signals.
Three different propagation delay times associated with a
logic gate:
tPHL: output changing from the High level to Low level
tPLH: output changing from the Low level to High level
tPD=(tPLH + tPHL)/2
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(average propagation delay)
Logic Gates
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18. Propagation Delay
A
B
C
In reality, output signals
Ideally, no
normally lag behind
input signals:
delay:
1
0
1
Signal for A
0
1
0
1
0
1
Signal for B
0
1
Signal for C
0
time
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Signal for A
Signal for B
Signal for C
time
Logic Gates
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19. Calculation of Circuit Delays
Amount of propagation delay per gate depends on:
(i) gate type (AND, OR, NOT, etc)
(ii) transistor technology used (TTL,ECL,CMOS etc),
(iii) miniaturisation (SSI, MSI, LSI, VLSI)
To simplify matters, one can assume
(i) an average delay time per gate, or
(ii) an average delay time per gate-type.
Propagation delay of logic circuit
= longest time it takes for the input signal(s) to propagate to the
output(s).
= earliest time for output signal(s) to stabilise, given that input
signals are stable at time 0.
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Logic Gates
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20. Calculation of Circuit Delays
In general, given a logic gate with delay, t.
t1
t2
:
tn
:
Logic
Gate
max (t1, t2, ..., tn ) + t
If inputs are stable at times t1,t2,..,tn, respectively; then the
earliest time in which the output will be stable is:
max(t1, t2, .., tn) + t
To calculate the delays of all outputs of a
combinational circuit, repeat above rule for all gates.
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Logic Gates
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21. Calculation of Circuit Delays
As a simple example, consider the full adder circuit where
all inputs are available at time 0. (Assume each gate has
delay t.)
X
Y
0
0
max(0,0)+t = t
max(t,0)+t = 2t
S
t
2t
max(t,2t)+t = 3t
C
Z
0
where outputs S and C, experience delays
of 2t and 3t, respectively.
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Logic Gates
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22. Universal Gates: NAND and NOR
AND/OR/NOT gates are sufficient for building any Boolean
functions.
We call the set {AND, OR, NOT} a complete set of logic.
However, other gates are also used because:
(i) usefulness
(ii) economical on transistors
(iii) self-sufficient
NAND/NOR: economical, self-sufficient
XOR: useful (e.g. parity bit generation)
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Logic Gates
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23. NAND Gate
NAND gate is self-sufficient (can build any logic circuit
with it).
Therefore, {NAND} is also a complete set of logic.
Can be used to implement AND/OR/NOT.
Implementing an inverter using NAND gate:
x
(x.x)' = x'
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x'
(T1: idempotency)
Logic Gates
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24. NAND Gate
Implementing AND using NAND gates:
x
y
(x.y)'
x.y
((xy)'(xy)')' = ((xy)')' idempotency
= (xy)
involution
Implementing OR using NAND gates:
x
y
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x'
((xx)'(yy)')' = (x'y')' idempotency
= x''+y'' DeMorgan
x+y
= x+y
involution
y'
Logic Gates
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25. NOR Gate
NOR gate is also self-sufficient.
Therefore, {NOR} is also a complete set of logic
Can be used to implement AND/OR/NOT.
Implementing an inverter using NOR gate:
x
(x+x)' = x'
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x'
(T1: idempotency)
Logic Gates
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26. NOR Gate
Implementing AND using NOR gates:
x'
x
y
y'
x.y
((x+x)'+(y+y)')'=(x'+y')'
= x''.y''
= x.y
idempotency
DeMorgan
involution
Implementing OR using NOR gates:
x
y
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(x+y)'
x+y
((x+y)'+(x+y)')' = ((x+y)')'
= (x+y)
Logic Gates
idempotency
involution
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27. Implementation using NAND gates
Possible to implement any Boolean expression using
NAND gates.
Procedure:
(i) Obtain sum-of-products Boolean expression:
e.g. F3 = xy'+x'z
(ii) Use DeMorgan theorem to obtain expression
using 2-level NAND gates
e.g. F3 = xy'+x'z
= (xy'+x'z)' '
involution
= ((xy')' . (x'z)')' DeMorgan
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Logic Gates
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28. Implementation using NAND gates
x
y'
(xy')'
x'
z
(x'z)'
F3
F3 = ((xy')'.(x'z)') ' = xy' + x'z
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Logic Gates
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29. Implementation using NOR gates
Possible to implement any Boolean expression using NOR
gates.
Procedure:
(i) Obtain product-of-sums Boolean expression:
e.g. F6 = (x+y').(x'+z)
(ii) Use DeMorgan theorem to obtain expression
using 2-level NOR gates.
e.g. F6 = (x+y').(x'+z)
= ((x+y').(x'+z))' ' involution
= ((x+y')'+(x'+z)')' DeMorgan
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Logic Gates
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30. Implementation using NOR gates
x
y'
(x+y')'
x'
z
(x'+z)'
F6
F6 = ((x+y')'+(x'+z)')' = (x+y').(x'+z)
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Logic Gates
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31. Implementation of SOP Expressions
Sum-of-Products expressions can be implemented using:
2-level AND-OR logic circuits
2-level NAND logic circuits
AND-OR logic circuit
A
B
F = AB + CD + E
C
D
F
E
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Logic Gates
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32. Implementation of SOP Expressions
NAND-NAND circuit (by
circuit transformation)
a) add double bubbles
b) change OR-withinverted-inputs to NAND
& bubbles at inputs to
their complements
A
B
C
D
F
E
A
B
C
D
F
E'
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Logic Gates
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33. Implementation of POS Expressions
Product-of-Sums expressions can be implemented using:
2-level OR-AND logic circuits
2-level NOR logic circuits
OR-AND logic circuit
A
B
G = (A+B).(C+D).E
C
D
G
E
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Logic Gates
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34. Implementation of POS Expressions
NOR-NOR circuit (by circuit
transformation):
A
B
a) add double bubbles
b) changed AND-withinverted-inputs to NOR
& bubbles at inputs to
their complements
C
D
G
E
A
B
C
D
G
E'
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Logic Gates
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35. Positive & Negative Logic
In logic gates, usually:
H (high voltage, 5V) = 1
L (low voltage, 0V) = 0
This convention – positive logic.
logic
However, the reverse convention, negative logic possible:
H (high voltage) = 0
L (low voltage) = 1
Depending on convention, same gate may denote
different Boolean function.
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Logic Gates
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36. Positive & Negative Logic
A signal that is set to logic 1 is said to be asserted, or
active, or true.
A signal that is set to logic 0 is said to be deasserted,
or negated, or false.
Active-high signal names are usually written in
uncomplemented form.
Active-low signal names are usually written in
complemented form.
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Logic Gates
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38. Integrated Circuit Logic Families
Some digital integrated circuit families: TTL, CMOS,
ECL.
TTL: Transistor-Transistor Logic.
Uses bipolar junction transistors
Consists of a series of logic circuits: standard TTL, low-
power TTL, Schottky TTL, low-power Schottky TTL,
advanced Schottky TTL, etc.
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Logic Gates
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39. Integrated Circuit Logic Families
TTL Series
Standard TTL
54 or 74
7400 (quad NAND gates)
Low-power TTL
54L or 74L
74L00 (quad NAND gates)
Schottky TTL
54S or 74S
74S00 (quad NAND gates)
Low-power
Schottky TTL
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Prefix Designation Example of Device
54LS or 74LS
74LS00 (quad NAND gates)
Logic Gates
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40. Integrated Circuit Logic Families
CMOS: Complementary Metal-Oxide Semiconductor.
Uses field-effect transistors
ECL: Emitter Coupled Logic.
Uses bipolar circuit technology.
Has fastest switching speed but high power consumption.
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Logic Gates
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41. Integrated Circuit Logic Families
Performance characteristics
Propagation delay time.
Power dissipation.
Fan-out: Fan-out of a gate is the maximum number of
inputs that the gate can drive.
Speed-power product (SPP): product of the propagation
delay time and the power dissipation.
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Logic Gates
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42. Summary
Logic Gates
AND,
OR,
NOT
NAND
NOR
Implementation of a
Boolean expression
using these
Universal gates.
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Drawing Logic
Circuit
Analysing
Logic Circuit
Given a Boolean
expression, draw the
circuit.
Given a circuit, find
the function.
Implementation
of SOP and POS
Expressions
Positive and
Negative Logic
Concept of Minterm
and Maxterm
Logic Gates
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