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IC Mask Design - IC Layout Acceleration Tool - DAC Conference, June 2010

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Claire O'Keeffe

IC Mask Design - The Experts in all aspects of IC Layout. DAC Conference, Anaheim, June 2010 IC Layout Acceleration Tool - HiPer DevGen

TechnologieBusiness
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Acceleration of Analog Physical Design HiPerDevGen™ - Structure Generation
Factors Driving the need for Analog Acceleration Shorter Product Development Times 1 Shrinking Process Geometries 2 EDA advancement on other areas of M/S Design 3
Shorter Product Development Times Average IC Product Development Times “We need to re-assess design tools and practices to ensure we can achieve right first time design in a reasonable timeframe, and thus reach profitability sooner.” Douglas Pattullo, Director Field Technical Support, TSMC Europe Early 1990’s cycle times 0 6 12 18 24 30 Today’s average cycle times 0 6 12 18 24 30 Shorter Product Development Times Faster Time to Market
Effects of Shrinking Geometries Companies are most concerned about the challenges of higher mask costs, greater design complexity, IP costs and availability, and inadequate EDA tools. Source: Kalypso Semiconductor Analysis 2009.
Effects of Shrinking Process Geometries Technology Cost Pressures As geometries shrink, mask and design costs go up TSMC’s wafer forecast shows a 40% CAGR (4x in 5 years) due to new designs in 90nm, 65nm and smaller Mask Costs ($M) Design Costs ($k) First pass silicon is an essential target for all semiconductor companies regardless of geometry 350nm 90nm 22nm Source: EETimes
Effects of Shrinking Process Geometries EDA Trends Development and support of Design Kits Hierarchical Verification Successful deployment of P&R Tools Can handle multi-million gate designs Use of greater processing power
Effects of Shrinking Process Geometries Transistor Count v Design Cycle Time Transistor Count Design Time 90nm 250nm 45nm Design cycle times at 90nm are increasing!! Why?? Analog Layout Design IS now a bottleneck!! Acceleration of this process is key
Analog Design – Bottleneck 1 Full automation approach has not gained traction Analog Automation has been a disappointment Difficult to set up Schematics need to be generated in defined formats Complicated to Constrain Analog designers like to retain control 2 Very difficult to automate analog layout due to the ‘artistic’ nature of the process 3
Analog Physical Design Automation What do users want? Create efficient device placements from user-provided constraints Do this in a matter of minutes Easy to set-up and use Compliments existing user environments Closely resemble handcrafted layout Allow designers to apply constraints to groups of devices Source: Jim Solomon, Founder Cadence
Our Approach Acceleration Recognition and Generation of Common Structures ,[object Object]
Current Mirrors
Resistor DividersOur Approach Correct by Construction ,[object Object]
DRC & LVS CleanConsistent High Quality ,[object Object],Is “Silicon Aware” ,[object Object],Analog Designers can easily tune the design ,[object Object],[object Object]
Quick & Easy Set-up Manufacturing Rules User friendly GUI for set-up of new technologies No CAD development required Instant generation of parameterized devices and structures 20 minutes for any new process Note: Tanner will provide technology set-ups free of charge
Features of HiPerDevGen™ Linear Process Gradients Mask Misalignment Implant Shadowing Photolithographic Invariance Current Flow Direction Antenna / VT Shift WPE User Tuning Functionally Aware Floorplan Estimations Guarantees Matching Layout Optimization Parasitic Aware HiPerDevGen™
Features of HiPerDevGen™ Accelerates Layout time Optimized for Yield Double Contacts / Vias Support for DFM User Tuning Functionally Aware Guarantees Matching Floorplan Estimations Parasitic Aware Layout Optimization HiPerDevGen™
Features of HiPerDevGen™ User Tuning Functionally Aware Floorplan Estimations Guarantees Matching Parasitic Aware HiPerDevGen™ Considers device and interconnect parasitics Optimal solution based on user specific parasitic requirements Layout Optimization
Features of HiPerDevGen™ User Tuning Functionally Aware Floorplan Estimations Guarantees Matching Layout Optimization Parasitic Aware HiPerDevGen™ Ensures user defined matching, parasitic and performance requirements Reduced Simulation Cycle
Features of HiPerDevGen™ Understands functional differences between structures User Tuning Functionally Aware Floorplan Estimations Guarantees Matching Layout Optimizatons Parasitic Aware HiPerDevGen™
Features of HiPerDevGen™ User Tuning Functionally Aware Layout Optimization Guarantees Matching Floorplan Estimations Parasitic Aware HiPerDevGen™ Prompt Floorplan Estimation
Features of HiPerDevGen™ User Tuning Functionally Aware Floorplan Estimations Guarantees Matching Layout Optimization Parasitic Aware HiPerDevGen™
Current Mirror Generation
Current Mirror Generation
Current Mirror Generation
Current Mirror Generation
Current Mirror Generation
Current Mirror Generation
Current Mirror Generation
Differential Pair Generation
Differential Pair Generation
Differential Pair Generation
Differential Pair Generation
Differential Pair Generation
Differential Pair Generation
Differential Pair Generation
Typical Op Amp Schematic
Typical SDL Flow– Op Amp
HiPerDevGen: Structure Recognition Recognition of Current Mirrors Recognition of Differential Pairs
HiPerDevGen Generation Generation of Current Mirrors Generation of Differential Pairs
Completed Op-Amp Total Layout time <1 hr !!

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IC Mask Design - IC Layout Acceleration Tool - DAC Conference, June 2010

  • 1. Acceleration of Analog Physical Design HiPerDevGen™ - Structure Generation
  • 2. Factors Driving the need for Analog Acceleration Shorter Product Development Times 1 Shrinking Process Geometries 2 EDA advancement on other areas of M/S Design 3
  • 3. Shorter Product Development Times Average IC Product Development Times “We need to re-assess design tools and practices to ensure we can achieve right first time design in a reasonable timeframe, and thus reach profitability sooner.” Douglas Pattullo, Director Field Technical Support, TSMC Europe Early 1990’s cycle times 0 6 12 18 24 30 Today’s average cycle times 0 6 12 18 24 30 Shorter Product Development Times Faster Time to Market
  • 4. Effects of Shrinking Geometries Companies are most concerned about the challenges of higher mask costs, greater design complexity, IP costs and availability, and inadequate EDA tools. Source: Kalypso Semiconductor Analysis 2009.
  • 5. Effects of Shrinking Process Geometries Technology Cost Pressures As geometries shrink, mask and design costs go up TSMC’s wafer forecast shows a 40% CAGR (4x in 5 years) due to new designs in 90nm, 65nm and smaller Mask Costs ($M) Design Costs ($k) First pass silicon is an essential target for all semiconductor companies regardless of geometry 350nm 90nm 22nm Source: EETimes
  • 6. Effects of Shrinking Process Geometries EDA Trends Development and support of Design Kits Hierarchical Verification Successful deployment of P&R Tools Can handle multi-million gate designs Use of greater processing power
  • 7. Effects of Shrinking Process Geometries Transistor Count v Design Cycle Time Transistor Count Design Time 90nm 250nm 45nm Design cycle times at 90nm are increasing!! Why?? Analog Layout Design IS now a bottleneck!! Acceleration of this process is key
  • 8. Analog Design – Bottleneck 1 Full automation approach has not gained traction Analog Automation has been a disappointment Difficult to set up Schematics need to be generated in defined formats Complicated to Constrain Analog designers like to retain control 2 Very difficult to automate analog layout due to the ‘artistic’ nature of the process 3
  • 9. Analog Physical Design Automation What do users want? Create efficient device placements from user-provided constraints Do this in a matter of minutes Easy to set-up and use Compliments existing user environments Closely resemble handcrafted layout Allow designers to apply constraints to groups of devices Source: Jim Solomon, Founder Cadence
  • 10.
  • 12.
  • 13.
  • 14. Quick & Easy Set-up Manufacturing Rules User friendly GUI for set-up of new technologies No CAD development required Instant generation of parameterized devices and structures 20 minutes for any new process Note: Tanner will provide technology set-ups free of charge
  • 15. Features of HiPerDevGen™ Linear Process Gradients Mask Misalignment Implant Shadowing Photolithographic Invariance Current Flow Direction Antenna / VT Shift WPE User Tuning Functionally Aware Floorplan Estimations Guarantees Matching Layout Optimization Parasitic Aware HiPerDevGen™
  • 16. Features of HiPerDevGen™ Accelerates Layout time Optimized for Yield Double Contacts / Vias Support for DFM User Tuning Functionally Aware Guarantees Matching Floorplan Estimations Parasitic Aware Layout Optimization HiPerDevGen™
  • 17. Features of HiPerDevGen™ User Tuning Functionally Aware Floorplan Estimations Guarantees Matching Parasitic Aware HiPerDevGen™ Considers device and interconnect parasitics Optimal solution based on user specific parasitic requirements Layout Optimization
  • 18. Features of HiPerDevGen™ User Tuning Functionally Aware Floorplan Estimations Guarantees Matching Layout Optimization Parasitic Aware HiPerDevGen™ Ensures user defined matching, parasitic and performance requirements Reduced Simulation Cycle
  • 19. Features of HiPerDevGen™ Understands functional differences between structures User Tuning Functionally Aware Floorplan Estimations Guarantees Matching Layout Optimizatons Parasitic Aware HiPerDevGen™
  • 20. Features of HiPerDevGen™ User Tuning Functionally Aware Layout Optimization Guarantees Matching Floorplan Estimations Parasitic Aware HiPerDevGen™ Prompt Floorplan Estimation
  • 21. Features of HiPerDevGen™ User Tuning Functionally Aware Floorplan Estimations Guarantees Matching Layout Optimization Parasitic Aware HiPerDevGen™
  • 36. Typical Op Amp Schematic
  • 38. HiPerDevGen: Structure Recognition Recognition of Current Mirrors Recognition of Differential Pairs
  • 39. HiPerDevGen Generation Generation of Current Mirrors Generation of Differential Pairs
  • 40. Completed Op-Amp Total Layout time <1 hr !!
  • 41. Summary Problem Analog Layout is now a bottleneck Automation attempts have not gained traction Solution HiPerDevGen adopts an acceleration approach Generates high quality “first time right” layout Is “Silicon Aware” and understands process artefacts Gives the user complete control over the design Simple to set-up and use No change in design flow methodology
  • 42. Come See for Yourself! View a HiPerDevGen™Demo Tanner – Booth #1342 Tanner EDA User Event Thursday 17th June 2010 For more information visit www.tannnereda.com

Notes de l'éditeur

  1. “We all need to re-assess design tools and practices to ensure we can achieve right first time design in a reasonable timeframe, and thus can all reach profitability sooner.”Douglas Pattullo, Director Field Technical Support, TSMC Europe