65nm and beyond CMOS designs are commonly implemented with “tapless” library cells which do not provide built-in n-well or substrate taps, improving cell density. This cell efficiency results in additional layout complexity for power-gating designs. Three well tapping methods are described for production powergating designs considering design schedule, leakage power, chip area and complexity.

1. WELL TAPPING METHODOLOGIES IN POWER-GATING DESIGN
Kaijian Shi1 and David Tester2
1 2
Cadence Design Systems, Dallas, USA and Structured Custom, Cambridge, UK
kaijians@cadence.com and david.tester@structured-custom.com
ABSTRACT The first method implements always-on tap cells to
65nm and beyond CMOS designs are commonly keep n-well biased at VDD when the design operates
implemented with “tapless” library cells which do not in the shutdown mode, i.e. power gated.
provide built-in n-well or substrate taps, improving cell The second method requires built-in taps in the PM
density. This cell efficiency results in additional layout cells to maintain well biasing of the PM cells when the
complexity for power-gating designs. Three well design is in the shutdown mode.
tapping methods are described for production power- The third method partitions the design into always-
gating designs considering design schedule, leakage on and shut-down regions. The PM cells are placed
power, chip area and complexity. exclusively in the always-on region to sustain required
n-well biasing.
I. INTRODUCTION
Each method has advantages and shortcomings.
Tapless designs have been popular in 65nm and
The choice of method depends on the considerations
beyond CMOS designs to increase cell density and
and priorities on leakage power, silicon utilization
silicon area efficiency. In tapless designs, the logic is
efficiency and implementation complexity.
implemented using cells which do not have built-in tap
contacts connecting n-well and p-substrate to power In the following part of the paper, the methods will
and ground rails in the cells. To prevent latch-up and be described in detail. Considerations for reliable
maintain proper transistor back biasing, tap cells production power-gating designs will be discussed.
which have built-in contacts to n-well and p-substrate Overheads and tradeoffs will be explained. Next, the
are inserted in the layout at required intervals to three methods will be compared in terms of impact on
connect n-wells to VDD and p-substrate to VSS, leakage power, silicon utilization efficiency and
based on design rules defined in the technology DRC implementation complexity. Finally, recommendations
file. The n-wells of tapless logic cells extend out of the will be provided for selection of a method based on
cell boundaries to ensure n-well connections when design goals and priorities.
the cells are placed next to each other. Consequently,
II. ALWAYS-ON TAP CELL BASED METHOD
n-well and p-substrate regions of the logic cells are
properly biased by power and ground supplies. The first method provides dedicated power supply
through the tap cells insertedin the design.. to n-wells using the tap cells to keep n-wells of the
design biased to VDD in shutdown mode. This
The tap insertion becomes complicated in power-
requires an always-on tap cell, since the normal tap
gating designs [1-6] where logic cells can be
cells are not powered in the shutdown mode.
powered-off while power management (PM) cells,
such as power switch cells, isolation cells, retention A. Always-on tap cell vs. normal tap cell
registers and always-on logic cells, must remain The normal tap cell is a simple design (Fig. 1a)
powered to maintain controllability and state retention which has two metal contacts; one connects n-well to
within the design. For power-gating designs that VDD rail and the other connects p-substrate to VSS.
implement header switches to shut off power supply, When the tap cells are inserted into a design, their
the main challenge is to maintain proper n-well bias in VDD and VSS rails are connected, by abutment, to
those logic cells that are powered-off and the PM cells the power and ground network of the design to
that remain alive. provide n-well bias. In the power-gating design, the
Three well tapping methods are described in this power supply to VDD rails is shut-off in the shutdown
paper, addressing challenges in power-gating designs mode. To maintain the power supply to the n-well, the
using tapless standard cells. The methods have been n-well contact in the tap cell must be separated from
applied successfully to production designs meeting the VDD rail and directly connected to the power
different design goals and priorities. supply. This design change is depicted in Fig. 1b
resulting in the always-on tap cell where the n-well

2. tap becomes a pin that can be connected to the chip logic never reaches close to ground because the
power supply. The p-substrate is still connected to switch cells are far from ideal and considerably leaky
a
VSS rail to maintain well bias as the VS rail remains
SS in 40nm node and beyond. Also, the size ratio is
A
connected in the shutdown mode. determined by IR-drop constraints and power density
of the design in normal oper ration mode. Table 1
shows the leakage penalty of always-on n-well
biasing from SPICE simulation of a small test case in
different technology nodes and Vth’s. Size ratio of the
switch to logic cells is 0.096.
Table I. Ioff in gated nwell vs always-on nwell
s.
Ioff_well_off Ioff
f_well_on
Node/Vth Ioff_ratio
Figure 1 a) normal tap cell, b) always-o tap cell
on (nA) (nA)
28HP/LVt 16.2 77.4 4.78
B. Method description 28HP/SVt 15.78 153.4 9.72
For a single domain power-gating design, the
g 28HP/HVt 12.9 57.65 4.47
always-on tap cells are inserted at the intervals
defined by the technology tapping rules. Then, the 40LP/LVt 0.169 1.06 6.27
n-well pins of the tap cells are routed to connect the 40LP/SVt 0.166 1.43 8.61
always-on VDD supply network in the design to get 40LP/HVt 0.143 1.05 7.33
constant power supply. Since n-wells of the tapless
logic cells are overlapped with adjacen cells in each
nt 65LP/LVt 0.082 0.443 5.40
row in the layout, forming continuing n-w wells in the cell 65LP/SVt 0.081 0.439 5.42
rows, the n-wells of the logic cells are biased by the 65LP/HVt 0.070 0.467 6.67
always-on VDD through the tap cells’ n- -wells.
The main advantage of the metho is that it is
od
simple to implement, leveraging the e existing normal In power-gating designs with both always-on and
tap insertion flow. It also results in highest silicon power gated power domains, th always-on tap cells
he
utilization efficiency compared with o other methods, are inserted in the power gated domains. For always-
d
due to no additional well spacing requ uirement in cell on domains, normal tap cells are use to avoid VDD
a
placement. Moreover, it does not impo constraints
ose power routing needed for always-on taps.
a An
on PM cell placement which helps phys sical synthesis. example of the method implem mented in a two power
However, the method incurs a leakage power penalty domain design is shown in Fi 2. The bottom left
ig.
in the shutdown mode because n-w wells of pMOS domain is always-on with norm tap cells inserted
mal
transistors are biased at VDD while the power supply
e aligned to the rails. Always-on taps were implemented
to the transistors is shutoff. This create a significant
es in the rest of the design with tap n-well pins
w
bias from n-well to drain and gate of p pMOS resulting connected to the always-on VDD straps next to them.
D
in higher junction and gate leakag in pMOS.ge
Consequently, the shutdown mode leakage of a III. TAP PM CELL BASED MET THOD
design can increase up to 10 times depending on For leakage critical designs, the leakage penalty in
technology nodes, Vth cell types and s size ratio of the the always-on tap cell based method might not meet
m
switch and logic cells. At smaller tech hnology nodes the leakage target. In that case, it is necessary to shut
,
this causes a higher leakage penalt due to the
ty off the power supply to the n-w taps. However, PM
well
thinner tox and hence larger well lea akage. On the cells are active in shutdown mode so n-wells in the
m
other hand, lower Vth logic cells ha ave a smaller PM cells must remain being biased at VDD to be
leakage penalty because the reductio of the sub-
on functional. To address this issue, the tap PM cell
threshold leakage from the reversed back biasing based method has been developed.
becomes more effective and the re elatively large The method implements sp pecially designed PM
leakage makes the n-well leakage co ontributing part cells containing built-in n-well taps that connect to
relatively less effective. As we look to th dependency
he their internal always-on power straps (Fig. 3) keeping
s
on the transistor size ratio of the sw witch and logic n-well biased in shutdown mode, This results in a
cells, a smaller ratio results in larger le
eakage penalty mixed tap and tapless design where PM cells are tap
w
due to lower shutdown voltage on the logic cells and cells and rest of the logic cells are tapless cells. In the
a
hence lower cell leakage and higher n-w leakage. It
well shutdown mode, the power su upply to the tap cells
is worth mentioning that the shutdown voltage on the inserted in the tapless design re egions is shut off which

3. Figure 3. Tap PM cell (double row)
Figure 2. Domain-based tap insertion e
example region based method describe in the next section.
ed
PM cells can be freely placed in optimal positions as
i
in turn shuts off power to the n-well of l
logic cells. The long as their always-on VDD pin can be routed to the
ns
n-well of the PM cells is biased through internal taps always-on power straps. Ho owever, the method
to the always-on VDD, maintaining norm operation.
mal requires custom PM cells and area wasted at left and
a
Since n-well of the PM cells is biased while right boundaries of the PM cell is significant lowering
surrounding n-well in the tapless lo ogic cells are silicon utilization efficiency cons
siderably since power-
shutoff, the n-well of PM cells can no longer overlap gating designs often impleme tens of thousands
ent
n-well in surrounding tapless cells. Well spacing switches, always-on buffers and isolation cells.
d
between PM cells and tapless cells m must satisfy the
hot-well spacing rule defined in the te echnology. It is IV. ALWAYS-ON REGION BAS SED METHOD
worth noting that the n-well of a tapless cell is This method has been developed to avoid the
extended beyond the cell boundary so n-wells of the leakage penalty of the first met thod and the design of
tapless cells are overlapped forming a continuous n- custom tap PM cells in the se econd method. In this
well. This tapless cell n-well extension w intrude into
will case, PM cells are all tapless cells requiring tap cell
the PM cell placed next to the tapless cell, and insertion to maintain n-well bias To address the need
s.
therefore must be considered in the ho ot-well spacing of separating n-wells of the PM cells from the n-wells
M
check. Consequently, PM cells need considerable
d of the logic cells, placement reg
gions, called always-on
space at cell boundaries, consuming s silicon area. In regions, are created exclusively for PM cells. Each
production designs, cells are common mirrored on
nly always-on region has its own dedicated always-on
adjacent rows and n-wells of cells in the mirrored rows
e VDD rails separated from rails outside the region. The
o
overlap. This is leveraged in designin the tap PM
ng n-well of the cells in the regio is connected to the
on
cells to occupy both mirrored rows to hide the n-wells always-on VDD through tap cells inserted in the
of the PM cell from the top and bott tom of its cell region. These always-on region are placed cross the
ns
boundaries and hence eliminate needs of the hot-well chip based on the prediction of the needs and
n
spacing at top and bottom to improve a area efficiency. positions of the PM cell ls in the physical
Fig. 3 shows an example PM cell. implementation. In the physic synthesis, the PM
cal
Only those PM cells that require pM MOS transistors cells are only allowed to be pla aced in the always-on
to be active in shutdown mode need bu uilt-in well taps. regions. An illustration example is shown in Fig. 4.
For those isolation-low cells which imp plement a pull- The always-on regions are shown in red. The top
s
down nMOS at the output, there is no need for the tap and bottom regions are for switc cells. The region on
ch
version cells, because pMOS transistors of the cell do the right is where the output iso
olation cells are placed.
not contribute to the isolation in the shhutdown mode The four regions in the middle of the block are created
o
and so isolation-low cells can be taplesss. to place always-on repeaters.
The main advantage of the method is low leakage Advantages of the method are low leakage power
a
power in shutdown mode, since n-we of the logic
ell in shutdown mode and no need to create the custom
d
cells are not biased. Impact on the physical tap PM cells. However, the method introduces
e
implementation is much smaller than the always-on
e considerable physical implem mentation complexity.

4. Moreover, the region creation and p placement are timing models of the tapless PM cells, as modification
M
highly design dependent and difficult to predict. It
t has minimal impact on fun nctional layout. Area
could often result in lower silicon utiliza
ation efficiency overhead of the method is usua less than 5%.
ally
and negative impact on design timing an routability.
nd The always-on region based method is much more
complicated to implement and less predictable in its
effect on the design. Moreove it often impacts the
er,
design timing and routability. The area overhead
varies with the quality of the always-on region
t
planning and could be significant. However, the
method does not introduce a leakage penalty, nor
requires development of custom PM cells.
m
The choice of the method depends on the design
d
goals and priority in terms of design performance,
f
leakage power, schedule, and silicon area. If
a
development schedule and pe erformance are higher
priorities than leakage power in shutdown mode, the
n
always-on tap based method is the choice. On the
other hand, for battery operated designs where
shutdown mode leakage is critic and area efficiency
cal
is less important, the tap PM cell based method is a
c
Figure 4. Always-on region based m
method good choice. In the case where design resources are
e
not available to create the tap PM cells, the always-on
P
An always-on region can be created by either an region based method is an alter rnative method.
exclusive region or a custom placeme site. In the
ent
former case, a special filler cell not containing n-well VI. SUMMARY
is needed at region boundaries to se eparate the n- Three well tapping methods have been developed
wells from outside. VDD rails in th region are
he to address the challenges in the tapless power-gating
e
assigned to the always-on VDD and s separated from designs. The methods are described with
a
rails outside of the region. implementation details. Each method has advantages
m
In practice, always-on region plannin is done after
ng and shortcomings which are discussed and
initial physical implementation to scope how many PM compared. The proper choice of the method depends
o
cells are needed and where they should be placed. on design goals and priorities in terms of design
Assuming PM cells can be clustered into regions, the performance, leakage power, development schedule,
d
always-on regions are created and pla aced based on and silicon area. The method have been applied
ds
size and position requirements. To ensu the regions
ure successfully to production pow wer-gating designs to
can hold the required PM cells, always- regions are
-on meet different design goals and priorities.
often created larger than actually needed. This
reduces silicon utilization efficiency. REFERENCES
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Always-on regions also add placeme constraints
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,
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M