The document discusses the Input/Output Buffer Information Specification (IBIS) model and its significance. [1] IBIS is an industry standard for modeling I/O buffers that provides accurate behavioral models without proprietary circuit information. [2] It was developed in the 1990s and is now maintained by the IBIS Open Forum comprising EDA vendors and computer manufacturers. [3] IBIS models allow faster simulations compared to SPICE models and enable signal integrity analysis across different EDA tools.

1. Seminar
Availability of IBIS model and its Significance
Shankardas Deepti Bharat
CGB0911002
VSD534
M. Sc. [Engg.] in VLSI System Design
Module Title: High speed board design
Module Leader: Mr. U. Mohan Roy
M. S. Ramaiah School of Advanced Studies 1

2. Agenda
Introduction
History
IBIS and useful
Significance
Buffer models
IBIS model file
Vendors
Future scope
Summary
Reference
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3. Introduction
• IBIS stands for Input/Output Buffer Information Specification
• Is a standard for describing the analog behavior of a buffer based on the
specification of current-voltage (I-V) characteristics, voltage-time (V-t)
characteristics, device package parasitic, input capacitance, and timing
measurement information for several types of I/O structures
• Accurately models a buffer’s behavior without revealing proprietary
information about the circuit’s structure or fabrication process
• Used to perform board level signal integrity simulations and timing
analyses
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4. History
• In 1990s developed by Intel corporation
• In June 1993 issued version 1.0
• In 1993 IBIS Open Forum created
• In 1995 IBIS Open Forum collaborated with EIA (Electronics Industries
Alliance)
• IBIS Open Forum
 Comprises EDA vendors, computer manufacturers, semiconductor
vendors, universities, and end-users which counts to 35 members.
 Proposes updates and reviews, revises standards, and organizes
summits
 Promotes IBIS models and provides useful documentation and tools
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5. Comparison
Table 2 SPICE vs. IBIS models
SPICE models IBIS models
It has all the information but includes It describes the electrical behavior of
circuit information so requires circuit without disclosing the
proprietary process. proprietary information
Computational efficiency is good computationally very accurate
Models are complex usually IBIS models are very simple hence
easy to process
Programs are large as it comprises Programs are smaller since it focus on
many information though it is not the electrical behavior
necessary
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6. Significance
• Enables portability between multiple electronic design automation
(EDA) software tools—allowing customers greater flexibility in
choosing EDA software integrating layout and simulation capabilities
• Provides competitive accuracy
• Completes simulations faster than SPICE models, allowing solution
space analysis through sweeps of multiple parameters in a timely manner
• Enables easy integration of package models into simulations
• Provides measurement information, enabling automation of signal
integrity and timing verification in EDA software
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7. IBIS model generation
Figure 1. IBIS model generation [2]
• Perform pre-modeling activities that includes deciding model’s complexity
determining voltage, temperature and process limits etc
• DATAs are obtained from the spice simulation from the V/I and V/T characteristic
graphs
• These data are converted in the IBIS model in the tabular format and IBIS file is
created
• This file is taken for test to “Golden Parser” also called as “ibischk3” which checks
the syntax and confirms that the data are in IBIS standard
• Then validation is done by simulating this file which validates the accuracy
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8. I/O buffer model
Output Pkg Pull down Ramp
Input Pkg Enable Pkg
Device info, Reference Pull up I/V
Threshold info, Ccomp, T info V, Ccomp, T info
Pull down I/V
Power Clamp
Power Clamp GND Clamp GND Clamp
Pull up Ramp
Input model Output model
Figure 2. I/O buffer models [3]
Except these data required for the output model other needed data are.
• Test load capacitive value (CREF)
• Test load resistive value (RREF)
• Test load pull-up or pull-down reference voltage (VREF)
• Output voltage measurement point (VMEAS)
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9. Types of buffers used in IBIS models
 I/O buffer
 Capable of driving high, low and can be placed in high impedance state
 Needs 4 set of tables
 with pull-up transistor (output in high state)
 with pull-down transistor (output in low state)
 two with output in high impedance state
 requires pull-up, pull-down, power clamp and GND clamp
 Output buffer
 Cannot be placed in high impedance state
 Needs only two set of tables
 With pull-up transistor (output in high state)
 With pull-down transistor (output in low state)
 Power clamp and GND clamp is not required
 Open – drain buffer
 Open – source model describes pulldown – only designs
 But pullup – only and pulldown – only designs are technically open drain
 To avoid this confusion open – source and open – sink buffers are introduced
 Open – source buffer
 Buffers source current when driving
 Contains pullup no pulldown
 Open – sink buffer
 Buffers sink current when driving
 Contains pulldown no pullup
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10. Buffer models
When gathering I-V data for
input buffers the same only
the variable voltage source
is placed on the input node.
Input buffers contain only
[POWER Clamp] and [GND
Figure 3. Input buffer model [3] Clamp] I-V data.
For output buffer GND
Clamp data is gathered via
a voltage sweep with the
voltage source referenced
to ground the POWER
Clamp data is gathered by
a voltage sweep with the
voltage source Vcc-
Figure 4. Output buffer model [3]
relative.
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11. Extraction of required data
Extraction I – V data from simulation
• The pull-up and pull-down data define the drive strength of the device.
• These curves are obtained by characterizing the two transistors in the output. The
pull-up data describes the I/V behavior when the output is in a logic high state
(PMOS transistor on).
• Pull-down data shows the dc electrical characteristics when the output is in a logic
low state (NMOS transistor on).
• Schematic should include any ESD or protection diodes.
• Schematic should also indicate if the power clamp and/or ground clamp diode
structures are tied to voltage rails (voltage references) different from those used by the
pullup and/or pulldown transistors.
Figure 5. Buffer model pull and pull down waveform[3]
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12. Extraction of required data
IBIS model file is divided into 3 – parts
•General information about the file itself and the component being
modeled
•The component’s name, pin-out and pin-to-buffer mapping
•Behavioral descriptions of each unique buffer design in that component
HEADER FILE: Includes general information's
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13. IBIS model file
Component name
Pin name and mapping
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14. Behavioral description
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15. Advantages of IBIS models
• IBIS models are accurate as it considers
 Non-linear aspects of I/O structures in the model parameters
 Package parasitic and ESD structures in the model parameters
• Simulation time for an IBIS model can run 25x faster as it is behavioral
model
• IBIS does not have non-convergence issues
• Can run on any Industry wide platforms as most EDA vendors support its
specification
• The models are very easy to create as can be obtained from simulation
data.
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16. Vendors
Table 1 List of vendors
Actel Corporation IBM Corporation
Advanced Micro Devices, Inc. Intel Corporation
Altera Corporation Lattice Semiconductor
Corporation
Analog Devices, Inc. LSI Corporation
Broadcom Corporation Maxim Integrated Products
Cirrus Logic, Inc. Micron Technology, Inc.
Cortina Systems, Inc. On Semiconductor
Cypress Semiconductor PMC-Sierra, Inc.
Corporation
Freescale Semiconductor SanDisk
Hynix Semiconductor, Inc. Texas Instruments, Inc.
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17. Future scope
• Changes to the IBIS specification are proposed through a buffer issue
resolution document (BIRD)
• The ATM task group, quality task group, and the Open Forum work
to improve the capabilities and quality of IBIS models
• Proposed Changes in IBIS
• The multi -lingual extension enables IBIS to work with existing
languages (SPICE, VHDL-AMS, and Verilog-AMS)
• Can add data for electromagnetic compliance (EMC) using ICEM
standard For EMC analysis and allow radial based function (RFB)
buffer models
• SPICE implementations for on die interconnect descriptions through
External Circuit linkages
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18. Conclusion
• IBIS has emerged as a well-established industrial modeling format
because it helps make available suitably accurate digital I/O models
for semiconductor devices
• IBIS models seem accurate, easy to generate, and compatible with a
wide range of simulation platforms
• From the point of view of a semiconductor vendor, IBIS is a standard
specification that has solved the issue of proprietary information
surrounding SPICE models
• IBIS has created a common Industry format for modeling using
Behavioral information
• Systems designers use IBIS models to perform board level signal
integrity simulations and timing analyses
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19. References
1. Bob Ross (2003) ‘IBIS Present and Future’ [White paper], 7th IEEE
Workshop on Signal Propagation on Interconnects, Siena Italy
2. Bob Ross (2005) ‘Practical Issues with IBIS Models’ [White paper],
Interconnectix Unit of Mentor Graphics Corporation, Portland
Oregon
• Michael Mirmak (2005) IBIS Modelling Cookbook: For IBIS Version
4.0. Washington DC: Government Electronics and Information
Technology Association and The IBIS Open Forum
• Syed B. Huq (2000) ‘Effective Signal Integrity Analysis using IBIS
Models’ High-Performance System Design Conference, Cisco
Systems, Inc
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20. Thank You
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21. Remarks
Sl. No. Topic Max. marks Marks
obtained
1 Quality of slides 5
2 Clarity of subject 5
3 Presentation 5
4 Effort and question handling 5
Total 20
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