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Challenges in Designing a Low Power Speech Processing SoC -a designer’s perspective S. Krishnakumar Rao C-DAC
Agenda ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
About C-DAC ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
C-DAC, Thiruvananthapuram ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
VLSI Design Group at C-DAC(T) ,[object Object],[object Object]
Why Low Power? ,[object Object],[object Object],[object Object],[object Object],[object Object]
Low Power Design - Application areas ,[object Object],[object Object],[object Object],[object Object]
Constraints in ASIC design ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
Technology & Process selection ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
Technology & Process: for Low Power ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
Technology & Process: for Low Power ,[object Object],[object Object],[object Object]
Selection of Hard IP: RAM & ROM ,[object Object],[object Object],[object Object],[object Object],[object Object]
Selection of Hard IP: NVM ,[object Object],[object Object],[object Object]
Selection of Hard IP : NVM ,[object Object],[object Object],[object Object],[object Object],[object Object]
Selection of Hard IP: Clock management ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
Low Power Design techniques ,[object Object],[object Object]
Low Power Design techniques ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
Clock gating CLK EN EN1 GCLK EN D Q
Clock gating ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
Data Gating
Data Gating ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
Power gating Courtesy: Cadence Design Systems
Power gating ,[object Object],[object Object],[object Object],[object Object],[object Object]
Voltage and Frequency scaling ,[object Object],Courtesy: Cadence Design Systems
Speech Processor Application
NAADA - Speech processor ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
“ NAADA ” integrates ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],OTP 128KB 1.2V ROM 32KB 1.2V SRAM 64KB 1.2V DSP Engine CPU Glue Logic Standard Cells ( 1.2V , 130nm,LL) DSP Engine Volt. Doubler
ASTRA – IP Portfolio ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
ASTRA – IP Portfolio ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
Thank You

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Ip so c-30sept2010