This is a brief introduction to a high level synthesis tool, GAUT version 2.4.3

1. Synthesis and Verification
of Digital Systems
By Daniel Gomez-Prado
Feb 2013
The slides were prepared for a class
introduction to GAUT version 2.4.3,
a high-level synthesis tool developed
at http://hls-labsticc.univ-ubs.fr/

2. GAUT’s main window
Exit
This Window
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3. GAUT’s main window
Compiler (C to CDFG)
Synthesis (CDFG to VHD)
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4. C to CDFG
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5. C to CDFG
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6. C to CDFG
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7. C to CDFG
Compile C into CDFG
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8. C to CDFG
View CDFG
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9. C to CDFG
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10. C to CDFG
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11. GAUT’s main window
Compiler (C to CDFG)
Synthesis (CDFG to VHD)
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12. CDFG to VHD
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13. CDFG to VHD
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14. CDFG to VHD
Set the desired Cadency
(must be multiple of clock)
Start with no-pipelining
Synthesize
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15. CDFG to VHD
VHD generated
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16. CDFG to VHD
FF 208
MUX 256
Registers and Muxes
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17. ./vhd2dot.pl volterra.vhd
---------- mux table
add0[a] (2) = reg_21 reg_19
add0[b] (8) = reg_21 reg_20 reg_19 reg_43 reg_37 reg_18 reg_25 reg_31
bus_1 (3) = reg_21 reg_17 reg_22
bus_2 (2) = reg_20 reg_18
bus_3 (1) = reg_19
mul2[a] (5) = reg_14 reg_15 reg_20 reg_0 reg_31
mul2[b] (7) = reg_2 reg_15 reg_17 reg_22 reg_16 reg_13 reg_7
mul3[a] (7) = reg_6 reg_17 reg_16 reg_22 reg_18 reg_4 reg_25
mul3[b] (7) = reg_14 reg_8 reg_1 reg_15 reg_20 reg_16 reg_11
mul4[a] (6) = reg_14 reg_22 reg_19 reg_16 reg_10 reg_25
mul4[b] (3) = reg_14 reg_15 reg_12
mul5[a] (7) = reg_14 reg_17 reg_19 reg_5 reg_16 reg_3 reg_18
mul5[b] (4) = reg_20 reg_22 reg_16 reg_9
reg_14 (1) = bus_3
reg_15 (1) = bus_2
reg_16 (1) = bus_1
reg_17 (1) = mul5[o]
reg_18 (1) = mul4[o]
reg_19 (2) = mul3[o] reg_18
reg_20 (2) = reg_19 mul2[o]
reg_21 (1) = add0[o]
reg_22 (2) = mul4[o] reg_20
reg_25 (1) = mul5[o]
reg_31 (1) = mul2[o]
reg_37 (1) = mul4[o]
reg_43 (1) = mul5[o]
---------- total muxes
5
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18. CDFG to VHD
FF 208
MUX 1024
Registers and Muxes
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19. ./vhd2dot.pl volterra.vhd
---------- mux table
add0[a] (8) = reg_14 reg_24 reg_19 reg_25 reg_21 reg_22 reg_18
add0[b] (9) = reg_24 reg_20 reg_15 reg_21 reg_17 reg_22 reg_26 mul2[a] (6) =
reg_14 reg_15 reg_20 reg_0 reg_18 reg_25
mul2[b] (7) = reg_2 reg_15 reg_17 reg_19 reg_16 reg_13 reg_7
mul3[a] (7) = reg_6 reg_17 reg_16 reg_19 reg_18 reg_4 reg_23
mul3[b] (7) = reg_14 reg_8 reg_1 reg_15 reg_20 reg_16 reg_11
mul4[a] (7) = reg_24 reg_14 reg_21 reg_19 reg_16 reg_10 reg_18
mul5[a] (7) = reg_14 reg_21 reg_17 reg_22 reg_5 reg_16 reg_3
reg_18 (5) = mul5[o] add0[o] mul4[o] mul2[o] mul3[o]
reg_21 (5) = add0[o] mul5[o] mul3[o] mul2[o] reg_19
reg_22 (4) = mul5[o] mul4[o] add0[o] reg_18
mul5[b] (4) = reg_20 reg_19 reg_16 reg_9
mul4[b] (3) = reg_14 reg_15 reg_12
reg_19 (3) = mul4[o] add0[o] mul3[o]
reg_14 (3) = add0[o] mul2[o] bus_3
reg_15 (2) = add0[o] bus_2
reg_16 (2) = mul4[o] bus_1
reg_17 (2) = mul5[o] mul2[o]
reg_20 (2) = reg_20 mul2[o]
reg_18 reg_23
bus_1 (3) = reg_14 reg_20 reg_18
bus_2 (3) = reg_14 reg_21 reg_16
bus_3 (1) = reg_22
reg_23 (3) = mul5[o] add0[o] mul3[o]
reg_24 (3) = add0[o] mul4[o] mul5[o]
reg_25 (2) = add0[o] mul2[o]
reg_26 (1) = mul2[o]
reg_23
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---------- total muxes
83

20. CDFG to VHD
Cannot synthesize with new cadence
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