Introducing OMAP-L138/AM1808 Processor Architecture and Hawkboard Peripherals
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Introducing OMAP-L138/AM1808 Processor Architecture and Hawkboard Peripherals
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- Welcome to the training module on Introducing OMAP-L138/AM1808 Processor Architecture and Hawkboard Peripherals.
- This training module will introduce Texas Instruments’ OMAP-L138/AM1808 Processor Architecture and Hawkboard Peripherals.
- The OMAP-L138 is a Low-power applications processor based on an ARM926EJ-S™ and a C674x DSP core. The dual-core architecture of the device provides benefits of both DSP and Reduced Instruction Set Computer (RISC) technologies, incorporating a high-performance TMS320C674x DSP core and an ARM926EJ-S core. The C674x DSP combines the performance of the C64x+ core with the floating-point capabilities and provides the extended precision necessary for high-precision algorithms on a variety of signed and unsigned 32-bit data types. The peripheral set includes: an Ethernet MAC (EMAC),one USB2.0 OTG interface, one USB1.1 OHCI interface, two inter-integrated circuit (I2C), one multichannel audio serial port (McASP), two multichannel buffered serial ports (McBSP), two SPI interfaces, four 64-bit general-purpose timers each configurable (one configurable as watchdog), a configurable 16-bit host port interface (HPI), up to 9 banks of 16 pins of general-purpose input/output (GPIO), three UART interfaces, two enhanced high-resolution pulse width modulator (eHRPWM) peripherals, and 3 32-bit enhanced capture (eCAP) module peripherals. The rich peripheral set provides the ability to control external peripheral devices and communicate with external processors.
- The PRU real-time subsystem is a collection of two RISC cores, each with its own instruction and data memory, and fast I/O. The RISC cores of the PRUSS run at half the ARM/DSP clock frequency and have access to other SOC resources (e.g. external memory, peripheral registers, system DMA, etc.). The PRUSS is fully-programmable and can be used to add differentiation to customer products . The PRUSS is well equipped to perform embedded tasks that require manipulation of packed memory mapped data structures. It can also efficiently handle system events that have tight real-time constraints.
- The PRUSS consists of the following blocks: two independent 32-bit RISC processors, each with 4KB of instruction RAM and 512 bytes of data RAM; an interrupt controller for system event handling; and a I/O interface with up to 30 input pins and 32 output pins per PRU core on the AM18x. The AM17x PRU does not support I/O pins but can still be used for a variety of purposes such as custom data movement schemes, custom timers, etc. Note that although PRU can only run from its dedicated instruction RAM, it can be reset and new code can be loaded. This allows you to use the PRU for multiple functions.
- The PRUSS provides several benefits. It can be used to extend connectivity and enhance peripheral capability on AM1x devices. Customers can implement special peripherals (e.g. 9-bit UART) and bus interfaces. The PRU can also be used to implement smart data movement schemes (e.g. circular DMA). The PRUSS can also be used as a smart power controller. Allowing you to turn switch off the clock to the ARM; only waking up the core when specific events are detected. The PRUSS can be used to offload data handling tasks from the ARM, freeing up those core for other tasks. The full programmability of the PRU allows customers to implement custom interfaces.
- Now let’s look at the rich peripheral set.
- The universal parallel port (uPP) peripheral is a multichannel, high-speed parallel interface with dedicated data lines and minimal control signals. It is designed to interface cleanly with high-speed analog-to-digital converters (ADCs) or digital-to-analog converters (DACs) with up to 16-bit data width (per channel). It may also be interconnected with field-programmable gate arrays (FPGAs) or other uPP devices to achieve high-speed digital data transfer. It can operate in receive mode, transmit mode, or duplex mode, in which its individual channels operate in opposite directions. The uPP peripheral includes an internal DMA controller to maximize throughput and minimize CPU overhead during high-speed data transmission. All uPP transactions use the internal DMA to feed data to or retrieve data from the I/O channels. The DMA controller includes two DMA channels, which typically service separate I/O channels. The uPP peripheral also supports data interleave mode, in which all DMA resources service a single I/O channel. In this mode, only one I/O channel may be used. Maximum clock is ¼ of the CPU clock. Each channel can access 16 data signals. These signals are allocated to the channels depending on the mode of the UPP. The throughput data shown are about 80% of the maximum theoretical through put to account for other system traffic. The uPP is pin multiplexed with the video port input, HPI, PRU Subsystem, EMAC RMII and LCD interfaces, but since pin muxing is programmable on a per pin basis, many configurations are possible to support several of these peripherals at once.
- Parallel ATA (PATA) design throughput has maximum data transfer to 133MBytes/Sec and was unable to increase transmission rate due to hardware limitation. This limitation birthed SATA. SATA has lower pin count, operates at a much lower signal level (500mW peak-to-peak), and is scalable with frequency. Gen3 is now delivering 6GBits/Sec raw bandwidth. SATA uses two bi-directional differential data lines. While one is being used to transmit data and the other being used for transmitting status. So the 1.5Gbits/Sec and 3Gbits/Sec of throughput is the throughput on the transmit differential data line only. Differential lines makes design more robust making it immune from noise and less susceptible to EMI. No skew issues exist as when you have a single data line. Lower pin counts implies lower complexity of board design and lower cost. The 8b/10b encoding increases the size of the data by 25% since an 8-bit data is encoded to a 10-bit data prior to transmission. This allows for sufficient 1-to-0 and 0-to-1 transition in the bit stream allowing for clock recovery and eliminating a high-frequency clock signal. Reliability and performance comes with a price tag. Also 8b/10b encoding scheme makes uses of a running disparity scheme, i.e., maintains the balance of 1’s and 0’s transmitted or DC Balanced. Running Disparity protocol also has transmission error capability, errors introduced on the bus altering disparity would be identified. Legacy Mode is not supported, i.e., does not have shadow task file registers, and command processing is performed based on AHCI operation. AHCI makes use of data structures and Frame Information Structure (FIS). However AHCI maintains the software compatibility with legacy software and complies with the ATA/ATAPI-7 PATA Command Execution specification. NCQ allows devices to execute commands not only out of order but also execute commands partially minimizing access latency. H/W assist allows the Device to control the onboard SATA Controller DMA to fetch data from AM18x memory. A Port Multiplier allows up to 15 devices to be attached to a single HBA Port and the SATA controller has the H/W support to enable that.
- In SD mode, 1-bit and 4-bit data buses are supported, as is SDHC (Class 2, 4, and 6 cards ranging from 4GB to 32GB have been verified up to 37.5MHz). In MMC mode, 1-bit, 4-bit, and 8-bit buses have been verified up to 26MHz. This peripheral should also support 1- and 4-wire SD cards and SDHC, but these configuration shave not yet been confirmed by TI.
- The EMIFA is one of two memory interfaces on AM1x devices. The EMIFA is used to interface with external memory devices including SDR-SDRAM, ASRAM, NAND Flash & NOR Flash. The CPU, EDMA, and other master peripherals use the EMIFA to access data in external memory. The EMIFA can interface with up to 128Mbytes of single data rate (SDR) SDRAM over a 16-bit bus. Configurable CAS latencies and memory timings allow the EMIFA to support a wide range of SDRAM devices. Through its asynchronous interface, the EMIFA can also connect w/o glue logic to memory devices like ASRAM, NAND Flash, and NOR Flash as well as ASICs and FPGAs. The EMIFA supports both 8- and 16-bit devices and it’s programmable cycle timings allow for a wide range of memory devices to be supported. For 8- and 16-bit NAND flash, the EMIFA supports 1-bit and 4-bit ECC.
- The DDR2/mDDR controller is one of two memory interfaces on AM18x devices. The DDR2/mDDR controller is used to interface with DDR2 and mDDR SDRAM devices. The CPU, EDMA, and other master peripherals use the DDR2/mDDR controller to access data and instructions in external memory. The DDR2/mDDR controller can interface with up to 512Mbytes of double data rate (DDR) SDRAM over a 32-bit bus. Configurable CAS latencies and memory timings allow the DDR2/mDDR controller to support a wide range of DDR SDRAM devices.
- The EMAC module on AM1x supports the standard RMII interface to connect with Ethernet PHYs. The MII interface is available on AM18x only, and only one EMAC interface (RMII or MII) can be enabled at a time because there is only one physical EMAC module. Both 10- and 100-Mbps speeds are supported at full- and half-duplex modes. A local CPPI memory is included to store EMAC packet descriptors. When connected to a multi-port switch PHY, the VLAN tag support allows the EMAC to discriminate between multiple virtual networks. A “Clause 22” MDIO interface is included to handle the configuration and management of connected Ethernet PHYs. Aside from the intended purpose of interfacing with ethernet PHYs, the EMAC module can also be used to enable communication between embedded processors that also have EMAC interfaces. This application is not officially supported.
- USB 2.0 h as built in PHY with UTMI interface. It supports all three speeds/devices via a 2.0 Hub when operating as a Host. As a Host it supports a Multi-point setup where multiple devices are connected via a Hub. It has dedicated hardware, USB_DRVVBUS, that is directly controlled by the USB controller, to enable/disable external power logic (charge pump). Endpoints 1 to 4 are all capable of handling all the four transfers. Endpoint 0 is serviced via CPU only. EPs 1 to 4 are serviced via CPU as well as DMA. A 4KBytes of FIFO RAM is available for user software to configure as application desires. DMA makes use of Descriptors and Multiple queues easing the use of scatter gather functionality and allowing multiple transactions to be queued. Without a support of queue, only a single transfer can be handled one at a time which is a burden for a busy CPU.
- USB 1.1 is an OHCI controller with an internal PHY. It supports both full speed and low speed in host mode only.
- Realistically, a 50MHz pixel-clock is supported across operating modes. The memory bandwidth has been successfully stress-tested with a continuous 75MHz pixel-clock, where concurrent activity is managed with priority settings. **** However, the datasheet spec for max pixel-clock frequency is the current performance limiter **** TI is evaluating whether this spec can be raised. There is a wiki article on LCDC throughput performance: http://tiexpressdsp.com/index.php/OMAP-L1x/C674x/AM1x_LCD_Controller_%28LCDC%29_Throughput_and_Optimization_Techniques
- The Enhanced High Resolution Pulse Width Modulators (eHRPWM) can effectively generating complex pulse width waveforms with minimal CPU overhead or intervention. There are three eHRPWMs available on AM1707, and two eHRPWMs on AM1808.
- The Enhanced Capture Module is essential in systems were accurate timing of external events is important. Some of the uses for eCAP include sample rate measurements of audio inputs, speed measurements of rotating machinery (for example, toothed sprockets sensed via Hall sensors), elapsed time measurements between position sensor pulses, period and duty cycle measurements of pulse train signals, and decoding current or voltage amplitude derived from duty cycle encoded current/voltage sensors.
- The HPI provides a memory-like interface where an external host can gain access to memory inside the AM1x. This can be used for boot purposes or to exchange data in a multi-processor system. The interface is similar to an asynchronous memory.
- The McASP is designed for audio applications. Each McASP module is highly configurable for format (data size and alignment) and supports multiple streams of synchronized serial data – thus multiple channels of audio can be transported simultaneously. AM1x includes McASP data FIFOs that are designed to relax real-time requirements (enhancement over previous devices). EDMA is the recommended resource to service McASP. Aside from the standard audio application, it’s possible to retask the McASP for other functions such as generating arbitrary waveforms at slow frequencies. For example, the McASP can be configured to operate at 50MHz with a single 32-bit slot; with this setup, a 1.56MHz (50MHz/32-bits) square wave can be created with 20ns of resolution for modifying the pulse-width (potential PWM). This application is not officially supported.
- The McBSP is designed to interface to a variety of serial industry standard devices. Receive and transmit are fully independent and have flexible programmability of clock, phase and frame behavior. The McBSP can work with TDM data streams of up to 128 channels. AM18x includes McBSP data FIFOs that are designed to relax real-time requirements by making the port less sensitive to DMA latencies.
- The Serial Port Interface is a synchronous serial input/output port that enables interfacing with external microcontrollers and EEPROMs. It can also be used to configure ADC’s, DAC’s display drivers, shift registers etc. Multiple SPI Modes are supported , like 3 pin, 4 pin with Chip Select , 4 pin with Enable and 5-pin. The SPI can be a master or slave.
- The UART is used to interface to peripheral devices or modems. The UART supports autoflow control signals (CTS and RTS) as well as modem control functions (DSR, DTR, RI, DCD). Through its frequency pre-scaler, multiple baud rates can be supported including: 9600, 14400, 19200, 38400, 57600, and 115200 . The UART also supports 13x and 16x oversampling.
- I 2 C module allows AM1x to communicate with other board components using a 2-pin shared bus in both Master and Slave configurations. The I2C specification is supported by a large number of manufacturers for common interoperability.
- The general-purpose input/output (GPIO) peripheral provides dedicated general-purpose pins that can be configured as either inputs or outputs. In addition, the GPIO peripheral can produce CPU interrupts and EDMA events in different interrupt/event generation modes.
- The device has 64-bit general-purpose timers that can be used to time events, count events, generate pulses, interrupt the CPU, and send synchronization events to the DMA. It has an interrupt/event enable/status register. Read Reset timer mode to reset the timer count when the counter registers are read. Reload registers to automatically update the Period register and restart the timer counter when the initial timeout Period is reached. Capture registers to record the counter value of a timer upon a timeout or external event. 8 Compare registers with individual interrupts that trigger when the counter matches the compare values.
- Now let’s look at the development tool - Hawkboard. The Hawkboard is an open-source community board that was developed by an external vendor using the OMAP-L138 processor. It’s intended to showcase the performance of the high-precision floating-point DSP with the flexible ARM9 processor in an ultra low-cost development environment. This development platform has all the basic components needed for full feature development and is support totally by the Hawkboard community at www.hawkboard.org.
- A brand new product, the XDS100v2 is a very inexpensive JTAG emulator solution. For less than $80, you get the capability to interact and control the AM1x. This emulator is powered by and works using USB, and is available from Spectrum Digital and Blackhawk. TI makes the design files available so you can EVEN BUILD YOUR OWN. If you have the board space available, one idea is to design this down onto your own product as a debugging section for development purposes. The XDS100v2 only works with CCS4 and later. For additional information, you can go to the wiki page shown here.
- Thank you for taking the time to view this presentation on “ Introducing OMAP-L138/AM1808 Processor Architecture and Hawkboard Peripherals ” . If you would like to learn more or go on to purchase some of these devices, you may either click on the part list link, or simply call our sales hotline. For more technical information you may either visit the Hawkboard or TI site, or if you would prefer to speak to someone live, please call our hotline number, or even use our ‘live chat’ online facility. You may visit Element 14 e-community to post your questions.