1. International Journal of Electronics and Communication Engineering & Technology (IJECET), ISSN 0976 –
6464(Print), ISSN 0976 – 6472(Online), Volume 5, Issue 4, April (2014), pp. 89-94 © IAEME
89
LOW BITRATE MODULATOR USING FPGA
Devanshi S. Desai1
, Dr. Nagendra P. Gajjar2
1,2
Department of Electronics & Communication Engineering, Nirma University, Ahemdabad, India,
ABSTRACT
Satellite MODEM(Modulator and Demodulator) is used in satellite communication system.
Space communication link is power limited. There are some satellite applications which require low
bit rate. Low bit rate MODEM is cost effective, power efficient and creates low error rate in
compare to high bit rate MODEM. Binary Phase Shift Keying (BPSK) modulation scheme is best
suited for satellite communication since it is power efficient and provides low bit rate. In this paper,
first BPSK modem is designed using System generator in MATLAB 2011a. With the help of
MATLAB system modelling, VHDL design is done and simulated using ModelSim Simulator in
Xilinx ISE 13.2. Then the same has been verified using Hardware in Loop Verification on Field
Programmable Gate Array (FPGA) board that is Spartan 3.
Keywords: BPSK Modulation, FPGA, Satellite MODEM, System Generator.
1. INTRODUCTION
A MODEM is one of essential block for any communication system. The function of the
satellite modem is to transform an input bit stream to a radio signal and vice versa [1]. Data speed
and Bit error rate (BER) performance are related with digital modulation schemes. Bit rate is used to
define speed of digital communication system and BER assesses full end to end performance of
system. Lower order modulation technique like BPSK modulation creates low error rate which is
good for long distance communication system.
The objective of this paper is to design low bitrate BPSK modulator which can be used for
satellite applications like deep space telemetry, navigation system etc. BPSK MODEM is first
designed using Xilinx system generator and simulink block set/MATLAB. Then design VHDL
algorithm for BPSK modulator which works on bit rate 1200 bps. Then this design is simulated on
ModelSim and then implemented on Spartan 3 kit.
INTERNATIONAL JOURNAL OF ELECTRONICS AND
COMMUNICATION ENGINEERING & TECHNOLOGY (IJECET)
ISSN 0976 – 6464(Print)
ISSN 0976 – 6472(Online)
Volume 5, Issue 4, April (2014), pp. 89-94
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2. International Journal of Electronics and Communication Engineering & Technology (IJECET), ISSN 0976 –
6464(Print), ISSN 0976 – 6472(Online), Volume 5, Issue 4, April (2014), pp. 89-94 © IAEME
90
2. BPSK MODEM MODELING USING SYSTEM GENERATOR
System generator is a DSP design tool from Xilinx that enables the use of the Math-Works
model based Simulink design environment for FPGA design[2]. That means it uses simulink blockset
as well as Xilinx blockset. It allows DSP to design with FPGAs, automatic generation of HDL code
starting from a Simulink model and also allows the user to create its own libraries.
2.1 System Generator Blockset
1. Gateway In: It makes an approach to the behaviour of a signal in hardware.
2. Gateway Out: It returns an approach of the behaviour of a signal in hardware to the simulation
mode.
3. System Generator: It provides control of the system and simulation parameters. It is used to
invoke the generated code
4. Mcode: It calls a Matlab .m file and executes it during simulation.
5. Mult: It is used for multiplication of its two inputs.
6. FIR: It simulates a FIR Filter making a call to the Matlab FDATool. which is Filter Design and
Analysis tool.
7. Direct Digital Synthesizer (DDS) Compiler: It generates sine and cosine signals.
2.2 Simulink Blockset
1. Bernoulli binary generator: It generates random binary data.
2. AWGN channel: It adds white Gaussian noise to the input signal. The input signal can be real
or complex.
3. Scope: oscilloscope used to visualize the outputs.
2.3 Simulation
Fig. 1 shows BPSK modem design using system generator. As shown in Fig. 1, BPSK system
is divided in three parts: a modulator block, a channel and a demodulator block.
First two carrier waves with phase difference of 180°, of specific frequency are generated by
DDS Complier. Then the carrier with 0° phase is assign to the output whenever input data is 1.
When input data is 0 then the output is assign carrier with 180° of phase. This process will result in
BPSK modulated output. Then the BPSK output passes through AWGN channel. It generates
distorted BPSK output.
Fig. 1: BPSK MODEM using System generator

3. International Journal of Electronics and Communication Engineering & Technology (IJECET), ISSN 0976 –
6464(Print), ISSN 0976 – 6472(Online), Volume 5, Issue 4, April (2014), pp. 89-94 © IAEME
91
In the process of demodulation, coherent detection is performed. The received BPSK
modulated data is multiplied with locally generated carrier frequency and passed through the 100 tap
FIR filter. This will give the clamped output which has binary non return to zero type coding pattern.
The resulting output is compared with zero to achieve the demodulation.
Fig. 2 shows the BPSK modulated output along with its demodulated output.
Fig. 2: BPSK Modulated and Demodulated Output
3. BPSK MODULATOR TESTING AND IMPLEMENTATION
3.1 Design & Test Methodology
Using MATLAB modeling of BPSK MODEM as a reference, VHDL code is written to
model BPSK modulator in Xilinx platform. The main blocks of BPSK Modulator are: Pseudo
random data generator, Direct Digital Synthesizer complier, Digital to analog (DAC) etc.
VHDL coding is done for individual modules and then individual simulation is done. Then
the whole design is synthesized and simulated using ModelSim Simulator. The simulation results are
compared with MATLAB’s simulation results which are used as golden reference.
Simulation process is done to ensure error free design before it will be implemented on
FPGA tool kit. Then same has been verified using hardware in loop verification and output will be
checked on Scope.
3.2 RTL Schematic View of BPSK Modulator
Fig. 3 shows Register Transfer Logic schematic of BPSK modulator.
Fig. 3: RTL Schematic view of BPSK Modulator

4. International Journal of Electronics and Communication Engineering & Technology (IJECET), ISSN 0976 –
6464(Print), ISSN 0976 – 6472(Online), Volume 5, Issue 4, April (2014), pp. 89-94 © IAEME
92
3.3 Implementation
Fig. 4 shows the principle of BPSK Modulator and Fig. 5 shows the principle of BPSK
Demodulator which are used for implementation on Spartan 3 kit.
Fig. 4: Principle of BPSK Modulator on FPGA
Fig. 5: Principle of BPSK Demodulator on FPGA
Pseudo random sequence is used as modulator source. This random sequence is generated by
using Linear Feedback Shift Register (LFSR) which do modulo-2 addition using tap method. Based
on the taps method, different Pseudo Noise (PN) codes are generated from LFSR.
DDS compiler generates sine signal and cosine signal using look up table method. In this
method, look up table is used to store sample values of sinusoidal signal. DDS complier generated
12 –bit sine and cosine signal which has sampling frequency 10 MHz and system clock is 400 MHz.
Sampling rate is 100 and analog signal frequency is 100 KHz. So that our system have bitrate 1200
bps.
When LSFR is ‘1’, output signal is sine signal and when LSFR is ‘0’ then output signal is
cosine signal. The BPSK modulated output is given to DAC block which is on Spartan 3 board in
order to sent through a channel and output can be seen on CRO scope.
The modulated siganl is affected by channel noise. The signal enters the demodulator with
the help of a ADC block (Analog to Digital Converter) which converts signal into a digital.
Then that digital signal is given to multiplier block where it multiply with the recovered
carrier signal which is generated internal in a ROM memory.
Demodulator block is little bit complex in compare to mod-ulator block. The reason is we
need to recover carrier signal and clock signal for synchronization. The output result from multiplier
is kept in an accumulator and com-pared with a decision threshold. So that the demodulated signal is
obtained.
ModelSim simulator tool is used to see output as waveform. This output gives idea about
phase shift and delay. Fig. 6 shows simulation output of BPSK Modulator and Fig. 7 shows
simulation output of BPSK Demodulator.

5. International Journal of Electronics and Communication Engineering & Technology (IJECET), ISSN 0976 –
6464(Print), ISSN 0976 – 6472(Online), Volume 5, Issue 4, April (2014), pp. 89-94 © IAEME
93
Fig. 6: BPSK Modulated Output on ModelSim
Fig. 7: BPSK Demodulated Output on ModelSim
After testing process, the BPSK modulator design has been verified using Hardware in
loop verification. Then implementation of design on FPGA tool kit is done. For that Spartan 3,
xc3s400-5pq208 is used. Fig. 8 shows BPSK modulated output on scope.
Fig. 8: BPSK Modulator Output on CRO

6. International Journal of Electronics and Communication Engineering & Technology (IJECET), ISSN 0976 –
6464(Print), ISSN 0976 – 6472(Online), Volume 5, Issue 4, April (2014), pp. 89-94 © IAEME
94
4. CONCLUSION
In this paper we proposed an implementation of the low bit rate BPSK System which is used
for satellite applications. BPSK MODEM is designed in the MATLAB using system generator. Both,
the modulating signal and the carrier are generated internally by DDS Compiler, the modulating
signal by a bernaulli generator. The modulated signal is obtained at the output of a mux block. Then
it is passed through a AWGN channel where white gaussian noise is added. Then BPSK modulated
signal is multiplied with carrier frequency and output is given to filter block. Then filtered output is
compared with a decision threshold.
The BPSK Modulator implemented on the Spartan 3 board which has the same principle as
the implementation in System Generator. VHDL algorithm is designed and then design is verified
using ModelSim Simulator tool. After the simulation process, same has been implementated on
Spartan 3 Board.
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