1. JTAG and System on Chip Testing Alexandru IOVANOVICI January 2011

2. TDI (Test Data In) TDO (Test Data Out) TCK (Test Clock) TMS (Test Mode Select) TRST (Test Reset) optional. The protocol is serial

4. More TAPS  scan chain;

5. JTAG adapter: at least level shifting, galvanic isolation

6. Host manipulates TMS and TDI and reads TDO

7. On top of this primitives are some higher level protocols for specific tests:

8. state switch;

9. Register shifting;

10. Free running;

12. Additional shift-register for each signal pin: path around device’s boundary  bypass of the IO and more visibility of the signals;

14. Similar capabilities found also in FPGAs and ASICs;

15. ARM11 core found inside many SoC:

17. Scan chain modification (IEEE1149.4)

18. Halt mode debugging:

19. Single threaded approach: (!!!) RT-systems

20. Monitor mode debugging:

21. Hardware exception: debug monitor routine

22. Core-specific extensions

23. Ie. ARM Core Sight, Infineon Nexus;

25. Atmel 16 bit: when there are enough pins to spare;

26. FPGA and CPLDs: for programming and debugging;

27. Many MIPS and PowerPCs;

28. PCI and PCIx connectors have pins;

29. Most of the boards have JTAG connectors (or just pads) to support testing during the manufacturing;

30. JTAG is used for field update of debugging;

31. Adapters in the range form 50 to 5000 USD (!!!)

32. PC parallel port bit-banging: cheap and slow 

34. Some manufacturer use more than the standardized four signals:

35. reset: tap RST and system RST;

36. Board voltage: level shifting;

37. GPIO lines;

38. USB/Ethernet: second chanel used for high speed tracing;

40. Chip Vendors: provide tools and custom adapters;

41. Tool Vendors: adapters for a broad range of chips;

42. OpenSource: GCC+GDB OpenOCD

43. Best support for ARM

44. Support for:

45. Stopping/halting;

46. Single step/instruction;

47. Breakpoint;

48. Data structure browsing;

50. Infineon Technologies AG;

52. Harddrive controller, ASIC, 250 kGates, 54mW;

53. Large SRAM: 80kB program SRAM, 8kB data SRAM;

54. Buffer DRAM: 8MBit for HDD data transfer; 20ns delay;

55. Specific elements:

56. PLL 400MHz;

57. PVT cell: analog;

58. Regulator: analog

60. Small and “simple” chip simple and cheap testing;

62. Small and fast vs. large and slow;

64. A single JTAG connector is the access point for all the tests;

65. Scan ATPG Test

66. Inputs are diagonal on the chip to allow parallel testing;

67. BIST capabilities: outsourced;

69. Large area of the SoC is covered by the SRAM;

70. MCU SRAM: coupled with the CPU;

71. HDC SRAM: HDD controller logic;

72. SRAM testing done with memory testers;

73. Test program stored in ROM and accessible for the tester;

75. Require external testing:

77. The BIST logic is tested with ATPG

78. Quiscustodiet ipso custodes ? 

79. Much longer than logic:

80. Paralell testing;

81. Using a dedicated memory tester;

83. 2ns, devide by 32;

84. Measured by ATE;

85. Dense layoiut vs. distributed layout;

86. Results indicate silicon speed;

87. track manufacturing process

89. Almost all mobile and embedded devices feature some SoC components:

90. Apple A4 is a SoC chip (ARM Cortex-A8 + PowerVR GPU);

91. Designer must know about testing:

93. Testing SoC Interconnects for Signal Integrity Using Boundary Scan;

94. Tehranipor M.H., Ahmed N., Nourani M.

96. Short signal paths, high speed;

98. Proposed solution:

99. Treating wires as modulesAdding boundary scan to wires (!!!)

101. Stuck-at;

102. Open;

103. Short;

104. One new JTAG instruction for reading test results;

105. Previous attempts:

106. Crosstalk testing;

108. Conventional serial boundary scan;

110. Extending JTAG to support interconnect testing;

112. multigigaHertz systems;

113. Voltage distortion and delay violation;

114. Causes:

115. Technological process variations;

116. Transmission line effects;

117. Coupling effects;

119. Maximum aggressor: crosstalk analysis on long lines;

121. Amplifier-based (Op-Amp);

122. Detecting voltage variations and delay thresholds;

123. Quite expensive;

124. Technological – less expensive – solutions do exist;

126. Testing SoC Interconnects using JTAG Test Architecture

128. ILS cell are twice expensive as the conventional ones;

131. An extension to IEEE1149;

132. SoC interconnect signal integrity loss;

133. Importance of the signall integrity justifies the investment in HW;

134. Authors propose a simple sensor but the method can be adapted for other sensors too;

135. Further research is needed for efficient compression patterns;