The one day workshop covers topics related to motor control applications using the TMS320F2812 microcontroller. It includes block diagrams of motor control systems, requirements of inverters, and an introduction to the TMS320F2812 microcontroller. The workshop outlines creating linker command files, system initialization procedures, and examples for LED blinking and using the PWM module.
7. Linker Function
Allocate the sections into the target configured
memory map.
Relocate the symbol and sections to assign them into
final address.
Resolved the undefined external references between
input files.
8. Memory Map
MEMORY
The MEMORY directive allows you to define the memory
map of a target system. You can name portions of memory
and specify their starting addresses and their lengths.
SECTIONS
The SECTIONS directive tells the linker how to combine
input sections into output sections and where to place these
output sections in memory.
9. Function
Memory Map Description
Name
Location
Size
Sections Description
Directsoftware section into named memory regions
Allows per file discrimination
Allows separate load/run locations
10. Compiler Section Names
Initialized Sections
Name Description Link Location
.text code FLASH
.cinit initialized global and FLASH
static variables
.econst constant data FLASH
(e.g. const int k = 3;)
.switch tables for switch statements FLASH
.pinit tables for global constructors (C++) FLASH
Uninitialized Sections
Name Description Link Location
.ebss global & static variables RAM
.stack stack space low 64Kw RAM
.esysmem memory for malloc functions RAM
11. Sections
Global Variable(.ebss)
int x = 2; Init Variables(.cinit)
int y = 7;
Void main(void)
{
long z; Local Variable(.stack)
z=x+y; Code(.text)
}
12. Example
0x00 0000 M0SARA 0x00 0400 M1SARA
M M
0x400 0x400
0x00 8000 L0SARA 0x00 9000 L1SARA
M M
0x1000 0x1000
0x30 0000 FLASH
0x4000
Placement Sections
.text into FLASH Block on PAGE 0
.ebss into MOSARAM on PAGE 1
.cinit into FLASH Block on PAGE 0
.stack into MOSARAM on PAGE 1
16. System Initialization
Oscillator, PLL and Clocking mechanisms,
Watchdog function and Low Power Mode
17. OSC and PLL Block
PLL and On chip oscillator provides the clocking signals for the device
and as well as control the Low Power Mode entry
XCLKIN OSCCLK PLL Diabled
0
On-
Chip CPU
OSC PLL /2 1
Bypass SYSCLKOUT
PLL
PLL Blok
4-bit PLL Select
20. Watchdog Module
Resets the C28x if the CPU crashes
Watchdog counter runs independent of CPU
If counter overflows, reset or interrupt is
triggered
CPU must write correct data key sequence to
reset the counter before overflow.
Watchdog must be serviced (or disabled)
within ~4.37ms after reset (30 MHz OSCCLK
for 150 MHz device)
21. Low-Power Modes Block
IDLE Mode - XNMI
STANDBY Mode - Any GPIOA
HALT Mode - XRS and GPIOA
24. ON CHIP MEMORY
0x00 0000 M0SARA 0x00 B000 L3SARA
M M
0x400 0x1000
0x00 0400 M1SARA 0x00 C000 L4SARA
M M
0x400 0x1000
System Description
TMS320F28335 0x00 8000 L0SARA 0x00 D000 L5SARA
M M
0x1000 0x1000
0x00 9000 L1SARA 0x00 E000 L6SARA
M M
0x1000 0x1000
L2SARA L7SARA
0x00 A000 0x00 F000
M M
0x1000 0x1000
25. Memory Placement section
.text into RAM Block L0123SARAM on PAGE 0 (PRG Memory)
.ebss into RAM Block L0123SARAM on PAGE 1(Date Memory)
.cinit into RAM Block L0123SARAM on PAGE 0 (PRG Memory)
.stack into RAM Block M1SARAM on PAGE 1 (Date Memory)
35. Pulse Width Modulation
PWM is a scheme to represent a signal as a
sequence of pulses
fixed carrier frequency
fixed pulse amplitude
pulse width proportional to instantaneous signal
amplitude
PWM energy ≈ original signal energy
36. Flexible PWM generation
Multiple PWM outputs with programmable
polarity.
Multiple independent PWM outputs from same
time base.
Individual trip zones for fault management.
Dead-band and chopping operation.
Shadow loading for glitch free operation.
51. EPWM Count Up Asymmetric Waveform
with Independent Modulation on EPWMA / B
52. Motivation for Dead-Band
Supply Rail
Gate Signal
Complementary PWM To power
Switching Device
Transistor gates turn on faster than they shut off
Short circuit if both gates are on at same time!
55. High Resolution PWM (HRPWM)
PWM Period
Regular PWM
Device Clock Step
(i.e. 100MHz)
(i.e. 10ns)
HRPWM divides a clock Calibration Logic tracks the
cycle into smaller steps number of Micro Steps per
ms ms ms ms ms ms
called Micro Steps clock to account for
(Step Size ~= 150ps) Calibration Logic variations caused by
Temp/Volt/Process
HRPWM
Micro Step (~150ps)