1. VLSI DIGITAL SIGNAL PROCESSING –
RESEARCH AREAS
Intelligence is the capacity to receive, decode and transmit
information efficiently. Stupidity is blockage of this process at any
point. Bigotry, ideologies etc. block the ability to receive; robotic
reality-tunnels block the ability to decode or integrate new signals;
censorship blocks transmission…Robert Anton Wilson
Shivoo Koteshwar - shivoo@pes.edu

2. Reference Material
 http://www.ee.umn.edu/users/parhi/
current_research.html
 http://www.advrg.wmin.ac.uk/about.html
 http://www.dspguru.com/
 http://sestevenson.wordpress.com/
 http://www.ee.umn.edu/groups/ddp/research.html
 http://www.ee.umn.edu/users/parhi/
past_research.html

3. Need
 Digital signal processing (DSP) applications are
becoming more prevalent in everyday use
 Because of this widespread usage and advances in
computer technology, the DSP algorithms themselves are
being subjected to more demanding specifications
 There is a constant need for designing systems with
lower power, higher speed (>100G bps), and lower
area
 Focus is on developing new algorithms, architectures,
techniques, and design tools

5. Example: DSP in Medical Field
 Involving use of advanced signal and image processing techniques in
classification of biomedical signals
 The objective here is to use signal processing for preprocessing and
feature extraction and use classifiers for classification.
 Applications include epilepsy detection and prediction, lung sound
signal processing, automated fundus eye scan analysis for diabetic
retinopathy and glaucoma screening, and detection of neural
disorders
 The work on language understanding of Schophrenic patients from
MEG signals
 Synthesis of various signal processing functions by chemical or
molecular reactions. These reactions are mapped to DNA strands.
The objective here is to synthesize molecular reactions for a specified
signal processing function. The emphasis is on design of robust
reactions that are (almost) rate-independent. This research is
expected to find applications in drug delivery and biosensing

6. Microprocessor and DSP Processor
 The 5 units (Memory, Instruction
Fetch, Instruction Decode, ALU
and Memory Access)
correspond to the four
different stages of processing,
which repeat for every
instruction executed on the
machine
 Processing Stages, Instruction
Fetch, Instruction Decode,
Execute and Memory Access
happens sequentially
Classical Von Neumann (vN) microprocessor
architecture - SISD (Single instruction single
data) type

7. Microprocessor and DSP Processor
 The sequential nature of the microprocessor architecture
makes it unsuitable for the efficient implementation of
computationally complex DSP systems, either in that it
cannot achieve the required sampling rate, or it meets
the requirement, but consumes a lot of power.
 The serial architecture is such that for data processing
applications, a lot of the transistors will not be
performing any useful part in the computation being
performed but are consuming power
 Microprocessors normally run large blocks of software,
such as operating systems, and usually are not used for
real-time computation.

8. Microprocessor and DSP Processor
 Until about 25 years ago, most signal processing was performed using
specialized analog processors. As digital systems became available and
digital processing algorithms could be implemented, the digital processing
of signals became more widespread.
 Initially, DSP was performed on general-purpose microprocessors such as
the Intel 8088. While this certainly allowed for more sophisticated signal
analysis, it was quite slow and was not useful for real-time applications
 In the 1980s, DSPm s such as the TMS32010 from TI emerged, which had
similar functionality to microprocessors, but differed in that they were based
on the Harvard architecture , with separate program and data memories
and separate buses
 In other words, they were microprocessor architectures which had been
optimized for DSP that perform multiply and accumulation operations,
consuming less power
 A more specialized design was needed
 A lot of changes in the original architecture have occurred since the
inception of DSP microprocessors

9. Characteristics of DSP Processor
 Are really just specialized microprocessors
 Designed to perform a fairly limited number of functions, but at very
high speeds.
 The digital signal processor must be capable of performing the
computations necessary to carry out the techniques like
transformation to the frequency domain, averaging, and a variety of
filtering techniques
 In order to perform these operations, a typical digital signal
processor would include the following elements:
1. Control processor
2. Arithmetic processor
3. Data memory
4. Timing control
5. Systems

10. DSP Microprocessor
Changes from original architecture
 Very Long Instruction Word (VLIW)
 Increased number of data buses
 Fixed point operation
 Bit-serial processing
 Pipelining
 Parallel processing
 Array processing – Systolic and Wavefront Arrays
 Reduced Instruction set computer (RISC)
 Multiprocessing
 Retiming

11. Characteristics of DSP Operations
 Computationally intensive
 Highly suited to implementation with parallel
processors
 Exhibits a high degree of parallelism, data
independent
 Have lower arithmetic requirements than other high-
performance applications, e.g. scientific computing

12. Comparing different DSP Processors
 Comparing the performance of DSPs is not always a straightforward procedure.
 While MIPS (million instructions per second) or MFlops (million floating-point
operations per second) are often used when comparing microprocessor speed, this is
not well suited to DSPs
 A common benchmark for comparing the performance of DSPs is the multiply and
accumulate (MAC) time
 The MAC time generally reflect the maximum rate at which instructions involving
both multiplication and accumulation can be issued. More meaningful benchmarks
would be computations such as FFTs and digital filters

13. Definitions
 Pipelining
 Reduce the effective critical path by introducing
pipelining latches along the critical data path
 Parallel Processing
 Increasesthe sampling rate by replicating hardware so
that several inputs can be processed in parallel and
several outputs can be produced at the same time
Datapath
pipelined
Parallel Processing

14. High-Speed/Low-Power VLSI Digital
Signal Processing Architectures
 The various wireless communication technologies have led to the tremendous increasing
demand for mobile processing devices which has intensive DSP and communication blocks
 Unlike wired devices that are optimized in favor of performance
 minimization of power/energy consumption while maintaining a certain level of performance is a critical
concern for wireless devices with limited energy capacity
 With continuous demand for increasing levels of performance, Digital processing techniques requires
high levels of computational throughput, particularly for real-time applications
 The trend in DSP design is toward more algorithm-based architectures. In other words,
the ease with which VLSI design can be done today leads the designer to more
specialized architectures.
 Research is focused on the voltage over scaling (VOS) techniques in DSP and
communication system design, such as filters, FFT/IFFT, etc.
 The VOS is one of the most prominent techniques that can significantly reduce the power consumption at
the cost of incurring computational error/noise due to timing violation.
 This is because as the supply voltage scales the power consumption decreases quadratically while the
delay increases linearly.
 Research is also in low-power architectures for biomedical applications. Specifically
efforts are directed towards low-power feature extractors and classifiers.

15. Broad Research Topics
 VLSI Digital Filters  Digital Integrated Circuit
 VLSI Speech and Image Chips
Coders  Error Control Coding
 Binary and Finite Field  Ultra Wideband Systems
Arithmetic Architectures  High Speed Transreceivers
 Design Methodologies for  3D Video Systems
Signal Processing Low-
 Soft Decision Reed-
Power
Solomon Decoder
 DSP System Design

16. VLSI Digital Filters
Concurrent Algorithms and architectures for VLSI Digital Filters exploit pipelining
or parallelism
 In 1960s and 1970s, digital signal processing
algorithms were implemented using the available
microprocessors which executed the algorithms
sequentially. Therefore, there was no motivation for
designing concurrent signal processing algorithms, which
could exploit pipelining or parallelism
 But today it’s a world of parallel processing. The efforts
are in
 Transforming existing non-concurrent algorithms into
concurrent forms to create pipelining and parallel
processing
 Designing new algorithms which are inherently concurrent

17. VLSI Digital Filters
Concurrent Algorithms and architectures for VLSI Digital Filters exploit pipelining
or parallelism
 Transforming non concurrent to concurrent: Look-ahead transformation,
decomposition, and incremental computation techniques
 Designing Inherently Pipelined System: Sum, delay, and product relaxed look-
ahead techniques
 Research Focus
 Design of pipelined and parallel recursive digital filters, recursive lattice digital filters,
recursive wave digital filters, LMS adaptive digital filters, adaptive lattice digital filters,
two-dimensional recursive digital filters, and rank-order and stack digital filters
 Examining Finite word-length effects in these filters for fixed-point hardware
implementations and introducing pipeline in these algorithms
 Pipelined stable recursive digital filters
 Pipelined architecture topologies for various forms of adaptive filters
 Recursive least square (RLS) adaptive filters
 Annihilation Reordering Look-Ahead recursive least square (RLS) adaptive filters can also
be pipelined based on Givens rotation; these filters maintain exact orthogonality. Truly
orthogonal IIR recursive filters have also been developed. These structures provide
excellent round-off noise properties.

18. VLSI SPEECH & IMAGE CODERS
 Achieving pipelining and parallel processing in
encoders and decoders used for speech and image
processing applications
 Because the processing of high-definition and super
high-definition television video signals requires very
high data rates
 Demands of the high-throughput real-time signal
and image processing application is the trend

19. VLSI SPEECH & IMAGE CODERS
 High-speed algorithms for predictive coders (including
differential pulse code modulation (DPCM), and
adaptive DPCM), Huffman and arithmetic decoders,
Viterbi decoders (which are variations of dynamic
programming computations), arithmetic coders, decision
feedback equalizers (DFEs), and adaptive DFEs
 Design of architectures for VLSI discrete wavelet
transforms which require fewer number of registers
using life time analysis
 Various approaches of implementations of DCTs
 Design approach to arbitrarily parallel Variable Length
Coder

20. Architectures for Binary and Finite Field
Arithmetic
 New architectures for arithmetic operations
 Goal is to save the number of pipelining latches
 Faster operation
 Complex designs - multiply-adder, shared divider/
square-root
 Arithmetic architecture design for finite field (i.e., Galois
field) which can be used in error control coding applications
 Appropriate scheduling techniques based on a hardware-
software co-design approach is also used
 Goal is low area, low latency and low power consumption

21. Design Methodologies for Signal
Processing
 Development of algorithms and design tools for rapid prototyping of these
algorithms using either dedicated VLSI chips or commercially available
programmable digital signal processors or using field-programmable systems
 Folding techniques to design any bit-serial architectures from digit-serial or bit-parallel,
and to design digit-serial architectures from bit-parallel ones which can be pipelined at
sub-digit levels
 Usual adhoc approaches limits the digit-size to be a divisor of word-length. Newer
techniques to accommodate arbitrary digit sizes
 Developing multiple rate signal processing algorithms – such as interpolation and
decimation
 In hardware system prototyping, we are concerned with high-level hardware
synthesis of specified algorithms for specified sample rate constraints, with the
objective of minimizing the number of functional units (such as adders, multipliers,
latches, buses, and interconnections etc.)
 Focus is on addressing systematic pipelining, retiming, unfolding of data-flow graphs
for unraveling the hidden concurrently in algorithms, addressing scheduling and
resource allocation for fixed multiprocessor architectures for software system
prototyping of signal processing problems, minimization of registers in data path,

22. Low Power DSP System Design
 Efficient power estimation tool development
 Power estimation for DSP circuits based on switching activity estimation
which incorporates glitching
 Various approaches to low-power arithmetic implementations are being
addressed
 New types of low power binary adders
 Various division, square-root and CORDIC architectures are being
evaluated for low-power consumption
 Approaches to power reduction in parallel FIR filters through novel
strength reduction
 Novel approaches to power reduction by gate resizing, supply
voltage scheduling and threshold voltage scheduling
 Low Power DSP system design approaches by pipelining of DSP
structures or novel arithmetic architectures

23. Digital Integrated Circuit Chips
 Focus is on layout design, fabrication and testing of IC
for demonstration of key algorithmic ideas
 4thorder recursive digital filtering which uses loop pipelining
and has 86MHz sample rate
 Fine grain pipelined chips - 16x16-bit multiplier which
makes use of internal redundant number representation,
and another one for a 100 MHz ADPCM video codec
 Shared divider/square-root chip
 Bit-level pipelined RLS adaptive filter
 Viterbi Coder chip
 Shared divider/square root and CORDIC chips

24. Error Control Coding
 Forward-error correction (FEC) codes can be used in
almost all kinds of communication systems (wireless,
wireline, fiber optic network, etc.) to provide significant
gains over the overall transmit power budget of the link,
and at the same time, lower the bit error rate.
 Research is on on both soft-decision and hard-decision
error control code
 e.g. Convolutional Viterbit and Turbo Codes, Block
Turbo Codes, LDPC Codes (a re-discovery), conventional
Convolutional Codes and Reed-Solomon Codes.

25. Error Control Coding
 JPL Turbo Code Homepage /  Wireless Multimedia Lab., Cornell
TDA Progress Reports University, USA.
 ANT Department of Communications  LNT Digital Communications Group
Engineering  Center for Satellite Engineering
 ITR's Turbo Coding Home Page, Univ. of Research (UK)
South Australia  David J. MacKay's Homepage, U.K.
 Small World Communications, Australia  Turbo Codes at West Virginia University,
 Turbo codes research at West Virginia West Virginia University, USA.
University  Jakob Anderson's Homepage, Technical
 Block Turbo Codes Home Page, ENST de University of Denmark.
Bretagne, France.  Patrick Robertson's Homepage, DLR,
 Wireless Systems Laboratory, Georgia Germany
Institute of Technology, USA.  Error Correcting Codes (ECC) Home
 Politecnico di Torino's Turbo-codes page Page,
 Technische Universität Lehrstuhl für  Coding Research Group, University of
Nachrichtentechnik München, Germany Notre Dame.
 Caltech Communications Group

26. Error Control Coding
 JPL Turbo Code Homepage: http://www331.jpl.nasa.gov/  LNT Digital Communications Group: http://www-nt.e-
public/JPLtcodes.html / technik.uni-erlangen.de/~dcg/Welcome.html
TDA Progress Reports: http://tda.jpl.nasa.gov/
progress_report/index.html  Center for Satellite Engineering Research (UK): http://
www.ee.surrey.ac.uk/CSER/DSP/turbo.html
 ANT Department of Communications Engineering: http://
www.comm.uni-bremen.de/pages/research.html  David J. MacKay's Homepage: http://wol.ra.phy.cam.ac.uk/
mackay/, U.K.
 ITR's Turbo Coding Home Page: http://www.itr.unisa.edu.au/
~steven/turbo/, Univ. of South Australia  Turbo Codes at West Virginia University: http://
www.csee.wvu.edu/~mvalenti/turbo.html, West Virginia
 Small World Communications: http://www.sworld.com.au/, University, USA.
Australia
 Jakob Anderson's Homepage: http://www.tele.dtu.dk/
 Turbo codes research at West Virginia University: http:// ~jda/, Technical University of Denmark.
www.csee.wvu.edu/~mvalenti/tc-webpages.html
 Patrick Robertson's Homepage: http://www.dlr.de/NT/NT-
 Block Turbo Codes Home Page: http://www-sc.enst- T/robertson/Welcome_us.html, DLR, Germany
bretagne.fr/turbo/principale.html, ENST de Bretagne,
France.  Error Correcting Codes (ECC) Home Page: http://imailab-
www.iis.u-tokyo.ac.jp/~robert/codes.html,
 Wireless Systems Laboratory: http://users.ece.gatech.edu/
~stuber/wsl.html, Georgia Institute of Technology, USA.  Coding Research Group: http://www.nd.edu/~eecoding/,
University of Notre Dame.
 Politecnico di Torino's Turbo-codes page: http://
hp0tlc.polito.it/turbo_codes.html
 Technische Universität Lehrstuhl für Nachrichtentechnik
München, Germany
 Caltech Communications Group: http://
www.systems.caltech.edu/EE/Groups/communications/
 Wireless Multimedia Lab: http://limburger.ee.cornell.edu/
wml/index.html, Cornell University, USA.

27. Ultra Wideband Systems
 As Ultra wideband (UWB) wireless communication has very
high data rates, ultra-low power consumption, robustness to
interference and fine ranging capabilities, it has been
chosen as candidate for different wireless personal area
network (WPAN) standards, including IEEE 802.15.3a and
802.15.4a.
 Research is on low power, area-efficient implementation of
different modules in digital baseband system in the wireless
UWB systems, including FFT/IFFT processors, time-domain/
frequency-domain equalizers, channel code decoders
(Viterbi decoders and LDPC decoders)
 Research to address the algorithms related to ranging,
geolocation, MIMO-UWB modulation and demodulation.

28. High Speed Transreceivers
 IEEE 802.310GBASE-T study group or IEEE-P802.3an Task Force, has
completed investigating the feasibility of transmission of 10 Gbps over 4
pairs of unshielded twisted pair (UTP) cables, and is developing its baseline
transmission scheme
 In this received signal at a receiver not only suffers from signal attenuation
and ISI but also suffers from echo, near-end cross talk (NEXT), far-end cross
talk (FEXT), and other noises such as alien NEXT (ANEXT)
 To meet the desired throughput and target BER requirements, we need to
perform significant amount of DSP operations in the transceivers, which
include channel equalization, channel coding, and echo/NEXT/FEXT
cancellation.
 Research focus is on high speed, low power and area-efficient
implementation of various DSP blocks used in 10GBASE-T Transceiver which
includes Parallel Decision Feedback Decoders, High speed Tomlinson-Harashima
precoders, Interleaved trellis coded modulation and decoding, Efficient long FIR
Adaptive Filter Implementation and Low Power Echo&Next Cancellers

29. 3D Video Systems
 Stereoscopic video is two-channel video taken
from a binocular camera which provides viewers
images with depth information. Recently the auto-
stereoscopic display becomes possible due to the
development of optical and LCD technology
 Opportunities exists in 3D motion estimation
improving techniques, improved disparity
matching for each pair of images and depth map
segmentation

30. Soft Decision Reed-Solomon Decoder
 Soft-Decision Reed-Solomon (RS) codes are of great interest in modern communications and storage
systems applications
 Koetter-Vardy (KV) soft-decision decoding algorithm of RS codes can achieve substantial coding gain
for high-rate codes, while maintaining a complexity polynomial with respect to the codeword length
 Present:
 In the KV algorithm, the factorization step can consume a major part of the decoding latency. A novel architecture based
on root-order prediction is proposed to speed up this step. As a result, the exhaustive-search-based root computation
from the second iteration of the factorization step is circumvented with more than 99% probability. In addition, resource
sharing among root-prediction blocks, as well as normal basis representation for finite field elements and composite field
arithmetic, are exploited to reduce the silicon area significantly.
 Applying the proposed fast factorization architecture to a typical (255, 239) RS code, a speedup of 141% can be
achieved over the fastest prior effort, while the area consumption is reduced to 31% In the architecture of the fast
factorization for the KV algorithm, the root computation and polynomial updating can be carried out simultaneously to
reduce the factorization latency further. The latency and area of the polynomial updating account for more than half of
the total latency and the total area of the factorization architecture, respectively.
 Future:
 Future work will address efficient implementations of polynomial updating. There is no real hardware implementation of
the entire KV algorithm so far. The only available implementation is for the interpolation step only, which uses four Xilinx
Virtex2000E devices and achieves a maximum clock frequency of 23 MHz. This implementation has overwhelming
complexity and runs too slow for practical applications. Current research is directed towards bringing down the
complexity of the KV decoding algorithm to practical level through further algorithmic and architectural level
optimizations.

31. Latest Research Areas
 Hardware Security: PUFs, Reverse Engineering
 DSP-based Voice-over-Internet Protocol
 Medical Field
 Seizure Prediction from EEG - A Pacemaker for the
Brain
 Automated Fundus Eye Scan Analysis

32. Hardware Security: PUFs, Reverse
Engineering
 The goal of this research is
 To use physical unclonable functions (PUFs) for
counterfeit prevention of integrated circuit chips and
devices
 To simultaneously authenticate devices and users
 The objective is to design PUF circuits based on
arbiter PUFs that cannot be hacked easily and to
include designing digital circuits that are harder to
reverse engineer

33. Seizure Prediction from EEG
 Epilepsy is the second most neurological disorders, which 0.6 to 0.8% of
people in the world suffer from.
 Approximately 75% of the patients with epilepsy achieve partial or
sufficient control over seizures from medication or resective surgery.
However, the remaining 25% of the patients do not have any treatment
currently available.
 If there is a way to predict occurrence of a seizure, it could sufficiently
enhance the therapeutic possibilities, leading to a better quality of life of
the patients.
 The general goal of this project is to propose a patient-specific algorithm,
which can predict occurrences of an epileptic seizure in advance.
 Specifically, this project intends to develop an algorithm to classify EEG
(electroencephalogram) signals before a seizure onset from those during ordinary
conditions with high sensitivity and a low rate of false positive
 In addition to predicting seizures, research is also focused on design of classifiers for
seizure detection

34. Automated Fundus Eye Scan Analysis
 Diabetic retinopathy is the leading cause of blindness in people of working age in
the developed world.
 The blindness due to diabetes costs US government and general public $500 million
annually. A WHO collaborative study projected that the global diabetic burden is
expected to increase to 221 million people by 2010
 However treatment can prevent visual loss from sight-threatening retinopathy if
detected early. In order to address the impact of diabetes, screening schemes are
currently being put into place based on digital fundas photography. However, the
cost of screening is expensive because of manual trained graders. Automating
detection is key to reduce cost and improve screening efficiency
 Current research interest is focused on automated diagnosis of diabetic retinopathy
using digital fundus images. The images will be graded onto diabetic retinopathy
scale (10 - 80 ) based on the type, quantity and the area of lesions present in the
eye. Feature extraction is the first step in the classification of these images. The
challenge lies in extracting robust features as the image color varies from patient to
patient.

35. Unchartered waters for many …
 Language Understanding of Schizophrenic Patients
 Attempts to understand language understanding at various levels in from
magnetoencephalogram (MEG) signals
 Molecular Signal Processing
 This research attempts to understand synthesis of DSP functions through
molecular reactions, where inputs and outputs are proteins or chemical molecules
 One example of implementation involves DNA strands.
 Synthesizing signal processing functions in biochemical and biomolecular systems
will enable biosensing, drug delivery, monitoring and controlling rate of therapy
or treatment
 Efforts are directed towards implementation of FIR and IIR digital filters, FFTs,
and equalizers using chemical reactions. Efforts are also directed towards
implementation of iterative computations through the molecular reactions
 Design Deep Brain Stimulation Therapy for Parkinsons and Dystonia
 Lung Sound Analysis

36. Other Research Areas
 Research into natural algorithms for fixed and adaptive  Development of high-fidelity decimators using polyphase
digital filtering. allpass filters.
 Development of fractional-delay filters for sample rate  Low-distortion wideband microwave amplifier design.
conversion and beamforming.
 Research into the suppression of harmonic distortion in
 Research in the area of modelling and design of wireless microwave transmission systems.
communication systems.
 Development of Global Positioning Satellite (GPS) receiver
 Development of new signal processing architectures and systems.
architectural component realisation in full-custom integrated
 Research into asynchronous logic techniques to realise low-
circuits.
power digital signal processors.
 Development of switched-capacitor filters for
 Research into flexible receiver structures and architectures
telecommunication applications.
for software radio applications.
 Development of IIR filter design techniques based upon
 Breaking the Nyquist barrier using non-equispaced sampling
balanced model truncation of much higher order FIR filters.
for radar applications.
 Development of computer-aided packages for the design of
 Computer-aided techniques for the design of RF and
discrete-time filters.
microwave filters.
 Evaluation of adaptive notch filters for tracking and
 Development of ultra-low-power digital signal processors
eliminating harmonic interference in mains-powered systems.
for use in digital hearing aids.
 Research into sigma-delta data conversion techniques for
 Research into high-quality digital image processing for
baseband and bandpass applications.
biomedical and urban traffic control applications
 Design and silicon implementation of bitstream codecs for
mobile telephone applications.

37. Project Ideas
 Software Configurable Global Positioning Systems Receiver silicon implementation
 Wireless FSK burglar alarm: algorithmic/structural/  GSM base station SD ADC: algorithmic/structural/
architectural design and gate array implementation architectural design, implementation and silicon integration
 Digital/switched-capacitor filters for integrated very low  Algorithmic/structural/architectural design, silicon
frequency, vehicle burglar alarm system integration and implementation of a mixed-signal, SD and
All pass polyphase based low-power CODEC, for use within
 Digital part of a SD CODEC: feasibility study and a Completely In Canal (CIC) digital hearing aid chip
architectural design for custom-silicon
 GNSScope: Platform for rapid prototyping and testing of
 Software Radio Cellular Base station System: Feasibility designs targeting multi-platform multi-frequency GNSS
Study, Design and Development systems
 Interactive Virtual Classroom  Ultra-low power configurable baseband processor for
 Software DAB Radio Receiver: design, implementation and GNSS algorithms
frequency synchronization in software  Adaptive IIR filtering techniques for channel equalization
 Linear mixed-signal SD CODECs for GSM base station: applications
design and implementation  Efficient frequency transformation algorithm and toolbox
 SD based fast hopping fractional-N frequency synthesizer: development
design and FPGA implementation  Low-power reconfigurable full-custom DSP processor design
 Programmable switched-capacitor ladder-filter chipset for and development
duplex modem systems complying with the CCITT magnitude  Novel frequency estimation algorithm development and
and group delay specification Implementation
 Oversampled PWM 28-bit DAC for very high fidelity audio  Adaptive schemes for non-linear distortion compensation in
applications: feasibility study and architectural design for communication systems
custom-silicon implementation
 ULTRA-low-power algorithm development for real-time
 Integrated SD based mixed-signal commander for mobile biomedical application
telephone systems: trouble-shooting and correction
 13-bit linear mixed-signal SD CODEC for GSM mobile
systems: algorithmic/structural/architectural design and

38. CONCLUSION
Digital Circuits and DSP are not yet outdated!
 Audio Signal Processing, Audio Compression, Speech processing, Speech
Recognition
 hi-fi loudspeaker crossovers and equalization, and audio effects for use with
electric guitar amplifiers
 Speech compression and transmission in digital mobile phones
 Room correction of sound in hi-fi and sound reinforcement applications
 Digital Image Processing, Video Compression
 Medical imaging such as CAT scans and MRI, MP3 compression, computer
graphics, image manipulation
 Digital Communication, RADAR, SONAR, Seismology
 Weather forecasting, economic forecasting, seismic data processing, analysis
and control of industrial processes
 Biomedical Signal Processing is another important area of research
 Signal Processing, Machine Learning and Classification are important tools for
biomedical signal processing – Feature extraction and classification is key here
 Monitoring, Diagnosis, Prevention and Therapy is driven by DSP
 Signal processing for monitoring and processing proteins

39. THANK YOU
Shivoo Koteshwar
9845722117
shivoo@pes.edu