2008 IEDM presentation

Record PVCR GaAs-based Tunnel Diodes Fabricated on Si Substrates using Aspect Ratio Trapping S. L. Rommel 1 , D. Pawlik 1 , P. Thomas 1 , M. Barth 1 , K. Johnson 1 , S. Kurinec 1 , A. Seabaugh 2 , Z. Cheng 3 , J. Li 3 , J. Park 3 , J. Hydrick 3 , N. Bai 3 , M. Carroll 3 , J. G. Fiorenza 3 , and A. Lochtefeld 3 1 Department of Microelectronic Engineering, Rochester Institute of Technology, Rochester, NY 14623 USA 2 Department of Electrical Engineering, University of Notre Dame, South Bend, IN 46556 USA 3 Amberwave Systems Corporation, Salem, NH 03079-4235 USA

[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],Outline

Tunnel Diode Characteristics and Applications V I P I V V P V V ,[object Object],[object Object],[object Object],[object Object],n+ p+   PVCR > 10 desired! ,[object Object],[object Object]

[object Object],[object Object],[object Object],Si Vs. III-V Tunnel Diodes Approach in this study: Integrate a III-V Esaki Diode on Si

[object Object],[object Object],[object Object],Si Vs. III-V Tunnel Diodes Approach in this study: Integrate a III-V Esaki Diode on Si High Speed Logic Memory

[object Object],[object Object],[object Object],Si Vs. III-V Tunnel Diodes Approach in this study: Integrate a III-V Esaki Diode on Si Si Esaki Diodes III-V Esaki Diodes

Silicon Ge SiO 2 500 nm J.S. Park et al., Appl. Phys. Lett 90 052113 (2007) ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],Aspect Ratio Trapping (ART) Defect Trapping

Aspect Ratio Trapping (ART) H W Ge Si ,[object Object],[object Object],[object Object],Aspect Ratio = H/W

[object Object],[object Object],[object Object],[object Object],Aspect Ratio Trapping (ART)

Coalesced Ge InGaAs/GaAs TD Strained InGaAs/top contact (Some layers are all InGaAs) Gold Contact GaAs/Ge heterointerface TEM image of Fabricated Device illustrates strained InGaAs diode layer. GaAs/InGaAs Device Concept Si Substrate Ge filled SiO 2 trenches

50 nm GaAs n-type (Si) >1x10 19 cm -3 10 nm In 0.1 Ga 0.9 As n-type (Si) ≥1x10 19 cm -3 80 nm GaAs p-type (C) >1x10 20 cm -3 TD1: Baseline Structure ,[object Object],[object Object],[object Object],[object Object]

Strained p-GaAs (C) Strained n-InGaAs (Si) QW, 10nm wide n-GaAs (Si) ,[object Object],[object Object],TD1: TEM image & SIMS profile

[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],Influence of Anneal on PVCR

[object Object],[object Object],[object Object],[object Object],TD1: I-V Characteristics

TD1: Temperature Response ,[object Object],[object Object],[object Object]

[object Object],[object Object],TD2: 20% In 50 nm GaAs n-type (Si) >9x10 18 cm -3 10 nm In 0.2 Ga 0.9 As n-type (Si) ≥9x10 18 cm -3 80 nm GaAs p-type (C) =5x10 19 cm -3 KEY POINT : Increasing In composition elevates current density and PVCR

[object Object],[object Object],TD3: All 10% InGaAs Esaki Diode 50 nm GaAs n-type (Si) >9x10 18 cm -3 10 nm In 0.1 Ga 0.9 As n-type (Si) ≥9x10 18 cm -3 80 nm In 0.1 Ga 0.9 As p-type (C) =5x10 19 cm -3 KEY POINTS : 250 A/cm 2

[object Object],[object Object],[object Object],TD4: Graded 10% InGaAs Esaki Diode 50 nm GaAs n-type (Si) >9x10 18 cm -3 10 nm In 0.1 Ga 0.9 As n-type (Si) ≥9x10 18 cm -3 80 nm GaAs p-type (C) =5x10 19 cm -3 10 nm gradedGaAs to In 0.1 Ga 0.9 As n-type 65 A/cm 2

Comparison with Devices in Literature

Conclusions ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]

RIT: R. Rafaelle, S. Hubbard, S. Polly, C. Bailey, and SMFL Staff Amberwave: M. Curtin, C. Major and the other lab staff Micron Technology: D. MacMahon (TEM imaging) Silvaco Corporation: TCAD software donation Project supported by National Science Foundation grants ECCS-0725760 and ECCS-0832653 Acknowledgements

2008 IEDM presentation

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