1. Calibration of ΣΔ Analog-to-Digital Converters
Based on Histogram Test Methods
A. Jalili and S.M. Sayedi J.J. Wikner, N.U. Andersson, and M. Vesterbacka
ECE Department Department of Electrical Engineering,
Isfahan University of Technology Link¨ ping University,
o
84156-83111 Isfahan, Iran SE-581 83 Link¨ ping, Sweden
o
Abstract—In this paper we present a calibration technique for In this work, a calibration technique for subADCs in
sigma-delta analog-to-digital converters (ΣΔADC) in which high- ΣΔADCs is proposed, then this technique is extended to also
speed, low-resolution flash subADCs are used. The calibration cover the imperfections of other building blocks, including
technique as such is mainly targeting calibration of the flash
subADC, but we also study how the correction depends on where DAC and accumulator. The technique employs so called
in the ΣΔ modulator the calibration signals are applied. histogram test methods [1]–[7] that are used to calibrate the
It is shown that the calibration technique can cope with errors converter. In these histogram-based methods an analog signal
that occur in the feedback digital-to-analog converter (DAC) and with a known probability density function (PDF) is applied to
the input accumulator. the input of the converter and then the number occurrences
Behavioral-level simulation results show an improvement of in
effective number of bits (ENOB) from 6.6 to 11.3. Fairly large of a certain digital output code is recorded. The result, i.e.,
offset and gain errors have been introduced which illustrates a the code density, is used to compute all bit transition levels
robust calibration technique. [2]. Linearity, gain and offset errors can be calculated and
Index Terms—Calibration, Comparator, Flash ADC, His- corrected for through these estimated transition levels.
togram based test methods, sigma-delta modulators.
I. I NTRODUCTION
Sigma-delta analog-to-digital converters, ΣΔADCs, are typ-
ically used in situtations where the input signal bandwidth
is small compared to the available sample frequency. Fig. 1
shows a block diagram of a first-order ΣΔADC including its
building blocks such as the flash analog-to-digital converter Fig. 1. A first-order ΣΔADC with output decimator omitted.
(subADC), feedback digital-to-analog converter (DAC) and
accumulator. The advantage with the ΣΔ approach is that
the subADC inside the modulator can be implemented with II. S TATIC E RROR M ODELS
a lower physical number of bits. For an (ideal) Lth-order ΣΔ A block diagram of a 4-bit flash ADC is shown in Fig. 2 (a).
modulator employing an M -bit subADC the achievable in- The structure contains 24 − 1 = 15 voltage reference levels
band signal-to-noise ratio (SNR) in dB is approximately generated by a resistor ladder. There is one comparator for
π 2L+1 each reference level, and the array of comparators compares
SNR ≈ 6.02 · M + 1.76 − 10 · log10 + the input signal with the reference voltages and generates a
2L + 1
fs thermometer code at its output. A decoder is used to generate a
+ (20L + 10) · log10 dB, more convenient representation, e.g., binary code, at the output
2fB
of the converter. The static errors affect the accuracy in the
where fs is the sample frequency and 2fB is the signal decision levels of the converter. Errors in the reference levels
bandwidth. By choosing the sample frequency and modulator are mainly caused by the resistor mismatch and offsets in the
order we can reach a high SNR, i.e., effective resolution. For comparators that can be model by a voltage source Vos of each
example, with M = 4, L = 1, and an oversampling ratio of comparator as shown in Fig. 2 (b).
fs /2fB = 64 we can achieve SNR ≈ 70 dB corresponding
to 11 effective number of bits, ENOB = (SNR − 1.76)/6.02. III. P ROPOSED CALIBRATION METHOD
Crudely, we can state that an 11-bit converter can be imple- In order to deal with different error sources in the ΣΔADC,
mented using a 4-bit converter running at higher speed. The we need to employ a calibration approach with minimum
subADC can then be, for example, implemented using a high- circuit topology dependence. Many of previously reported
speed architecture like the flash ADC, which normally would calibration techniques of flash ADCs [8]–[12], need to impose
not be applicable for an 11-bit converter due to increase in some changes to the ADC structure and especially comparators
hardware cost as function of number of bits. to perform calibration. This means that the calibration path
978-1-4244-8971-8/10$26.00 c 2010 IEEE

2. Fig. 3. The employed histogram-based calibration method in a first-order
ΣΔADC.
other offset values.
If the PDF generator circuit generates a signal with a uni-
Fig. 2. (a) Block diagram of a 4-bit flash converter. (b) Modeling of the form distribution, e.g., a ramp signal, in the range [−VR , VR ],
static errors as a voltage source Vos . we have for an ideal 4-bit converter and for every N input
samples:
Ni = N/16, for i = 1, 2, . . . , 16 (2)
will be confined to the flash subADC only and it is thereby
difficult to extend the calibration method towards the entire and for a 4-bit non-ideal converter for interval Ii (Fig. 4(b)
ΣΔADC. However, the histogram based technique is a proper for uniform PDF) we have:
candidate.
˜ 2VR /16 − Vos,i + Vos,i−1
The employed method in a first-order ΣΔADC is shown Ni = · N. (3)
2VR
schematically in Fig. 3. fin (x) and fout (x) are the PDF’s of
Rearranging (3) results in
the input and output signals of the subADC, respectively. Volt-
age VR is the reference voltage such that −VR < Vin < VR . ˜
Vos,i = Vos,i−1 − 2VR · Ni − Ni /N. (4)
During calibration mode, the output of the PDF generator is
Equation (4) is a recursive relationship that can be used in
connected to the input of the flash ADC. The PDF generator
the estimation of the offset values. Vos,0 = Vos,16 = 0, so for
produces an analog signal with a known PDF, fin (x). In
comparators number 1 and 15, eq. (4) results in
practice, due to the static errors, the input and output PDFs,
fin (x) and fout (x), are not identical, and in the histogram- ˜
Vos,1 = −2VR · (N1 /N − 1/16) (5)
based techniques, the differences are used to extract the
subADC errors. and
˜
Vos,15 = 2VR · (N16 /N − 1/16), (6)
In an ideal converter, with zero error sources, interval i is
defined as respectively. Equations (5) and (6) provide two initial condi-
Ii : x ∈ [Vr,i−1 , Vr,i ], (1) tions for the recursive expression in (4). One of the conditions
is sufficient for the calculations; however, in order to avoid
where Vr,0 = −VR , and Vr,16 = +VR . In practice, these
large additive errors during error estimation, offset errors
intervals are changed due to the static error sources.
related to comparators number 2 to 7 are estimated by using
If, within a certain period of time, N input samples in
initial condition (5) and offset errors related to comparators
the range [−VR , VR ] are applied to the ADC, the samples
number 8 to 14 are estimated by using initial condition (6).
would ideally be allocated to the intervals Ii identical to the
In the case of large offset values, as shown in Fig. 4 (d), it is
values of the input PDF. In a non-ideal case the numbers
possible that the reference levels cross each other. In this case,
differ from the ideal ones due to static error sources. The
interval Ii disappears and a new interval is created. To extend
difference between the wanted number of samples, Ni and
˜
the measured Ni can be used to estimate the error values.
Fig. 4 clarifies what happens to the different intervals, Ii ,
when we go from an ideal converter to a converter with static
errors in the reference levels. In Fig. 4 (a) we find the ideal
case. Ni out of N recorded samples belong to interval Ii .
Fig. 4 (b) then shows how the intervals will shift and also
contain a different number of samples, for example interval
˜
Ii will now contain Ni samples (with ∼ denoting the non-
ideal case). The difference between the wanted Ni and the
˜
measured Ni can be used to estimate the error values. Fig. 4(c)
illustrates the boundary intervals of the PDF which are used Fig. 4. The number of samples in (a) interval Ii in an ideal converter, (b)
to estimate the offset of first and last comparators in the array. interval Ii in a non-ideal converter, (c) intervals I1 and I16 in a non-ideal
These offsets are used as initial conditions to calculate the converter, (d) overlap of the reference levels due to large error values.

3. the estimation process towards such a condition, (4) can be
modified as follows:
˜
Vos,i = Vos,i−1 + 2VR · Ni + Ni /N. (7)
In case of an overlap, (7) must be used instead of (4). The
trimming process, i.e., the compensation of the estimated error
values merged in the comparator offset, can be done in various
ways [8], [9], [11]. In this work, an original trimming scheme,
reported in [8], is used where the offset of comparators is
compensated for by adjusting the reference voltages switched
in from the resistor ladder. So, after calibration of the flash
subADC, we have an accurate ADC, where the accuracy of
the calibration will depend on the trimming procedure and
calibration time. Disregarding that for now, the subADC can
be used to calibrate other error sources in the structure of the
ΣΔADC. Fig. 5. Suggested calibration of the DAC using the already calibrated flash
subADC.
A. Extending Towards DAC Errors
The output of an ideal binary coded 4-bit DAC can statically remain in their positions. In this case, the estimated offset of
be expressed as: comparator 2 is
4
Vos,2 = γDAC,2 · VLSB + δDAC , (11)
VDAC = −VR + VLSB · Di · 2i−1 , (8)
i=1 where γDAC,2 is the second LSB gain error of the DAC.
where Di ∈ {0, 1} are the input digital bits, VR is the reference Continuing this approach, the offsets of comparators 4, 8, and
voltage considering the signal range equal to [−VR , VR ] and 3 result in:
VLSB = 2VR /16 is the quantization step. In practice, the output Vos,4 = γDAC,3 · VLSB + δDAC , (12)
of the DAC deviates from its ideal value given in (8) according Vos,8 = γDAC,4 · VLSB + δDAC , (13)
to the offset and gain errors as:
4
and
i−1 Vos,3 = (γDAC,1 + γDAC,2 ) · VLSB + δDAC , (14)
VDAC = δDAC − VR + VLSB · Di · (2 + γDAC,i ), (9)
i=1 where δDAC,3 and δDAC,4 are the second MSB and MSB gain
where δDAC and γDAC,i for i = 1, 2, 3, 4 are the offset and gain errors of the DAC, respectively. Subtracting (14) from the sum
errors of the DAC, respectively. In order to estimate the error of (10) and (11) results in
values of the DAC, its output is directly fed to the input of δDAC = Vos,1 + Vos,2 − Vos,3 . (15)
the subADC. In this case, the corresponding estimated offset
value is the error (gain and offset) of the DAC. The concept After estimation of the DAC offset according to (15), the DAC
is shown schematically in Fig. 5 for a binary weighted DAC. gain errors can be calculated using (10) to (13). The DAC can
Five comparators numbered 1, 2, 3, 4, and 8 are chosen from be trimmed using for example a subDAC and/or some digital
the bank of the comparators and their threshold voltages can be predistortion techniques.
generated either from the reference ladder or the DAC. For a B. Extending Towards Accumulator Error
thermometer-coded DAC, we would require more comparators
to be used. During calibraton of the DAC, each time one After calibration of the DAC, the only remaining uncali-
of the threshold voltages of the mentioned comparators are brated block is the accumulator (including its summation of
generated by the DAC and through this the equivalent DAC DAC and input signals). In order to perform calibration for
errors can be estimated in terms of offset of these comparators. this block, the input test signal is applied at the input of the
The calibration phase of the DAC is as follows: First, the DAC ΣΔADC. Fig. 6 shows this concept. If the PDF generator,
input word, {D4 , D3 , D2 , D1 } is set to 0001 and switch S1 generates a signal with uniform distribution in the voltage
is put in position 2. The other switches (S2 to S5 ) remain in range [−VR , VR ], at the input of the ΣΔADC, a close-to-
their default position 1. In this case, the estimated offset of uniform distribution is obtained except that the boundaries
comparator 1 is: close to −VR and VR , as illustrated in Fig. 6, are attenuated.
The same formulas given for a uniform distribution can be
Vos,1 = γDAC,1 · VLSB + δDAC , (10) used but with minor modifications. The terms γacc and δacc
are the accumulator gain and offset errors, respectively. In this
where γDAC,1 is the LSB gain error of the DAC. Now the
case, the estimated offset values of the flash subADC result in
input {D4 , D3 , D2 , D1 } is set to 0010, switch S1 is put back
to position 1 and S2 is put in position 2. The other switches Vos,i = γacc · Vr,i + δacc , (16)

4. After calibration
12 Before calibration
10
ENOB (bit)
8
6
4
0 10 20 30 40 50 60 70 80 90 100
Simulation index
Fig. 6. Calibration of the accumulator gain error by applying the test signal
at the input of the ΣΔADC. Fig. 8. ENOB of the first-order ΣΔADC before ( ) and after ( ) applying
the proposed calibration technique.
where γacc is the accumulator gain error δacc is the accumulator
offset error and Vr,i is the reference voltage of the ith com- V. C ONCLUSIONS
parator. Equation (16) can be used to estimate the accumulator In this paper, we have extended an ADC calibration method-
gain error as: ology, previously employed for Nyquist-rate flash ADCs, to
γacc = Vos,9 − Vos,7 / Vr,9 − Vr,7 . (17) also cover calibration of ΣΔADCs. The calibration method,
using histogram-based methods, was extended to also cater
After calibration of accumulator gain error, the offset error can and correct for errors in the feedback DAC and input accu-
be calculated on average as: mulators of the ΣΔADC. The algorithms and test circuitry
15 were implemented on a behavioral-level in MATLAB and
1
δacc = Vos,i . (18) simulation results of a first-order ΣΔADC showed that nearly
15 i=1 full performance could be obtained after calibration.
IV. S IMULATION R ESULTS
The ΣΔADC of Fig. 1 is modeled behaviorally with a
4-bit flash subADC and DAC converters. The test setup is
shown in Fig. 7 where we have also included the decimation R EFERENCES
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