VlSI Lecture04
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VlSI Lecture04
- 1. Design and Implementation of VLSI Systems (EN1600) lecture04
- 2. Lecture 03: CMOS fabrication http://www.appliedmaterials.com/HTMAC/animated.html
- 3. Fabricating one transistor UV light Mask oxygen exposed Silicon dioxide photoresist photoresist oxide Silicon substrate Oxidation Photoresist Mask-Wafer Exposed Photoresist (Field oxide) Coating Alignment and Exposure Photoresist Develop RF RF RF RF Po Po Po we we Po we rr we Dopant gas r Ionized CCl4 gas r Ionized oxygen gas Ionized CF4 gas Silane gas photoresist oxygen e oxide oxide at oxide polysilicon g ly gate oxide po Oxide Photoresist Oxidation Polysilicon Polysilicon Etch Remove (Gate oxide) Deposition Mask and Etch Scanning ion beam Contact Metal silicon nitride holes contacts t sis top nitride G drain re G G G ox S D S D S D S G D S D Ion Active Nitride Contact Metal Implantation Regions Deposition Etch Deposition and Etch
- 4. Top view Source Gate Drain Polysilicon Source Gate Drain Polysilicon SiO2 SiO2 p+ p+ n+ n+ n bulk Si p bulk Si
- 6. Start with P substrate
- 7. 1. Spin Resist Coating
- 8. 2. Expose N Well Mask
- 10. 4. Implant N Well
- 11. 5. Remove Resist
- 12. Anneal wafer to diffuses N well (heal lattice) and grow new oxide layer
- 13. Remove oxide from anneal
- 14. 1. Spin Resist
- 15. 2. Expose resist with active diffusion mask
- 17. 4. Grow oxide on exposed surface
- 18. 5. Strip resist
- 19. Grown thin oxide over silicon surfaces
- 20. 1. Deposit poly using Chemical Vapor Deposition (CVD)
- 21. 2. Spin resist 3. expose resist using the GATE mask 4. develop resist 5. etch poly
- 22. Remove thin oxide layer where exposed
- 23. 1. Spin resist 2. expose with P implant mask 3. develop resist 4. implant P 5. strip resist
- 24. 1. Spin resist 2. expose with N implant mask 3. develop resist 4. implant N 5. strip resist
- 25. Remove resist – anneal wafer – oxide etch
- 26. Grow oxide 1. spin resist 2. expose Contact mask 3. develop resist 4. etch contacts 5. strip resist
- 27. 1. Deposit metal L1 2. spin resist 3. expose metal L1 mask 4. develop resist 5. etch metal 6. strip resist
- 28. Rest of metal layers follow similarly
- 29. Printing masks
- 30. The printer Illuminator optics Excimer laser (193 nm ArF ) Reticle library (SMIF pod interface) Beam line Wafer transport Operator system console Reticle stage Wafer stage Auto-alignment system 4:1 Reduction lens NA = 0.45 to 0.6
- 31. Photolithography is used to print desired patterns on the wafer UV light Reticle field size 20 mm 2 15mm, 4 die per field masks 5:1 reduction lens Image exposure on Serpentine wafer 1/5 of reticle stepping field pattern 4 mm 4 3 mm, 4 die per exposure Wafer The feature size directly depends on the wavelength of your lithographic system
- 32. Cross section of a 7-metal layer IC Next time: How to print different gates?