Wi Fi documantation

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CHAPTER 1
1. INTRODUCTION
1.1 Introduction to VLSI
The first digital circuit was designed by using electronic components like vacuum tubes
and transistors. Later Integrated Circuits (ICs) were invented, where a designer can be able to
place digital circuits on a chip consists of less than 10 gates for an IC called SSI (Small Scale
Integration) scale. With the advent of new fabrication techniques designer can place more than
100 gates on an IC called MSI (Medium Scale Integration). Using design at this level, one can
create digital sub blocks (adders, multiplexes, counters, registers, and etc.) on an IC. This level is
LSI (Large Scale Integration), using this scale of integration people succeeded to make digital
subsystems (Microprocessor, I/O peripheral devices and etc.) on a chip.
At this point design process started getting very complicated. i.e., manually conversion from
schematic level to gate level or gate level to layout level was becoming somewhat lengthy
process and verifying the functionality of digital circuits at various levels became critical. This
created new challenges to digital designers as well as circuit designers. Designers felt need to
automate these processes. In this process, Rapid advances in Software Technology and
development of new higher level programming languages taken place. People could able to
develop CAD/CAE (Computer Aided Design/Computer Aided Engineering) tools, for design
electronics circuits with assistance of software programs. Functional verification and Logic
verification of design can be done using CAD simulation tools with greater efficiency. It became
very easy to a designer to verify functionality of design at various levels.
With advent of new technology, i.e., CMOS (Complementary Metal Oxide Semiconductor)
process technology. One can fabricate a chip contains more than Million of gates. At this point
design process still became critical, because of manual converting the design from one level to
other. Using latest CAD tools could solve the problem. Existence of logic synthesis tools design
engineer can easily translate to higher-level design description to lower levels. This way of
designing (using CAD tools) is certainly revolution in electronic industry. This may be leading
to development of sophisticated electronic products for both consumer as well as business

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1.2 IC Design Flow

Specification
SPECIFICATION
s
Behavioral Description

Behavioral Simulation

Behavioral simulation
Behavioral
Behavioral

Constraints

Simulation

Synthesis

RTL Description
RTL Description
Functional
Functional
simulation
Simulation

Layout

Constraints

Logic
Synthesis
Gate Level netlist
Gate level Net
list
Automatic
P&R
Layout
Layou

t
Fabrication

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Lib
Lib

Logic simulation
Logic simulation

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1.3 Introduction to VHDL
VHDL is acronym for VHSIC hardware Description language. VHSIC is
acronym for very high speed Integrated Circuits. It is a hardware description
language that can be used to model a digital system at many levels of abstraction,
ranging from the algorithmic level to the gate level.
The VHDL language can be regarded as an integrated amalgamation of the following
languages:
 Sequential language
 Concurrent language
 Net-list language
 Timing specifications
 Waveform generation language - VHDL
This language not only defines the syntax but also defines very clear simulation
semantics for each language construct. Therefore, models written in this language can be verified
using a VHDL simulator. This subset is usually sufficient to model most applications .The
complete language, however, has sufficient power to capture the descriptions of the most
complex chips to a complete electronic system.

1.3.1 History
The requirements for the language were first generated in 1988 under the VHSIC chips for the
department

of

Defense

(DOD).

Reprocurement

and

reuse

was

also

a

big issue. Thus, a need for a standardized hardware description language for the design,
documentation, and verification of the digital systems was generated. The IEEE in the December
1987 standardized VHDL language; this version of the language

is known as the IEEE STD

1076-1987. The official language description appears in the IEEE standard VHDL language
Reference manual, available from IEEE. The language has also been recognized as an American
National Standards Institute (ANSI) standard. According to IEEE rules, an IEEE standard has
to be reballoted every 5 years so that it may remain a standard so that it may remain a standard.
Consequently, the language was upgraded with new features, the syntax of many constructs was

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made more uniform, and many ambiguities present in the 1987 version of the language were
resolved. This new version of the language is known as the IEEE STD 1076-1993.

1.3.2 Capabilities
The following are the major capabilities that the language provides along with the features that
the language provides along with the features that differentiate it from other hardware languages.
 The language can be used as exchange medium between chip vendors and CAD tool users.
Different chip vendors can provide VHDL descriptions of their components to system designers.
 The language can be used as a communication medium between different CAD and CAE tools
 The language supports hierarchy; that is a digital can be modeled as asset of interconnected
components; each component, in turn, can be modeled as a set of interconnected subcomponents.
 The language supports flexible design methodologies: top-down, bottom-up, or mixed. It
supports both synchronous and asynchronous timing models.
 Various digital modeling techniques, such as finite –state machine descriptions, and Boolean
equations, can be modeled using the language.
 The language is publicly available, human-readable, and machine-readable.
 The language supports three basic different styles: Structural, Dataflow, and behavioral.
 It supports a wide range of abstraction levels ranging from abstract behavioral descriptions to
very precise gate-level descriptions.
 Arbitrarily large designs can be modeled using the language, and there are no limitations
imposed by the language on the size of the design.

1.3.3 Hardware Abstraction
VHDL is used to describe a model for a digital hardware device. This model specifies the
external view of the device and one or more internal views. The internal view of the device
specifies functionality or structure, while the external view specifies the interface of the device
through which it communicates with the other modules in the environment.In VHDL each device
model is treated as a distinct representation of a unique device, called an Entity. The Entity is
thus a hardware abstraction of the actual hardware device. Each Entity is described using one
model, which contains one external view and one or more internal views.

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Architecture Body
An architecture body using any of the following modeling styles specifies the internal details of
an entity.
 As a set of interconnected components (to represent structure)
 As a set of concurrent assignment statements (to represent data flow)
 As a set of sequential assignment statements (to represent behavior)
As any combination of the above three.

Structural style of modeling
In this one an entity is described as a set of interconnected components. Such a model for the
HALF_ADDER entity, is described in a n architecture body
Architecture ha of ha is
Component Xor2 Port (X, Y in BIT; Z out BIT)
End component
Component And2
Port (L, M in BIT; N outBIT)
End component
Begin
X1 Xor2portmap (A, B, SUM)
A1 AND2portmap (A, B, CARRY)
End ha
The name of the architecture body is ha .the entity declaration for half adder specifies the
interface ports for this architecture body. The architecture body is composed of two parts the
declaration part and the statement part. Two component declarations are present in the
declarative part of the architecture body.
The declared components are instantiated in the statement part of the architecture body using
component instantiation. The signals in the port map of a component instantiation and the port
signals in the component declaration are associated by the position.

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1.3.4 Dataflow Style Of Modeling
In this modeling style, the flow of data through the entity is expressed primarily using concurrent
signal assignment statements. The data flow model for the half adder is described using two
concurrent signal assignment statements .In a signal assignment statement, the symbol <=implies
an assignment of a value to a signal.

1.3.5 Behavioral Style Of Modeling
The behavioral style of modeling specifies the behavior of an entity as a set of statements that are
executed sequentially in the specific order. These sets of sequential statements, which are
specified inside a process statement, do not explicitly specify the structure of the entity but
merely its functionality. A process statement is a concurrent statement that can appear with in an
architecture body.

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CHAPTER 2
2. INTRODUCTION TO HDL TOOLS
2.1 Simulation Tool
2.1.1 Active HDL Overview
Active-HDL is an integrated environment designed for development of VHDL, Verilog,
and EDIF and mixed VHDL-Verilog-EDIF designs. It comprises three different design entry
tools, VHDL'93 compiler, Verilog compiler, single simulation kernel, several debugging tools,
graphical and textual simulation output viewers, and auxiliary utilities designed for easy
management of resource files, designs, and libraries.

2.1.2 Standards Supported
2.1.2.1 VHDL
The VHDL simulator implemented in Active-HDL supports the IEEE Std. 1076-1993
standard.
2.1.2.2 Verilog
The Verilog simulator implemented in Active-HDL supports the IEEE Std. 1364-1995
standard. Both PLI (Programming Language Interface) and VCD (Value Change Dump) are also
supported in Active-HDL.
2.1.2.3 EDIF
Active-HDL supports Electronic Design Interchange Format version 2 0 0.
2.1.2.4 VITAL
The simulator provides built-in acceleration for VITAL packages version 3.0. The
VITAL-compliant models can be annotated with timing data from SDF files. SDF files must
comply with OVI Standard Delay Format Specification Version 2.1.
2.1.2.5 WAVES
Active-HDL supports automatic generation of test benches compliant with the WAVES
standard. The basis for this implementation is a draft version of the standard dated to May 1997
(IEEE P1029.1/D1.0 May 1997). The WAVES standard (Waveform and Vector Exchange to

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Support Design and Test Verification) defines a formal notation that supports the verification
and testing of hardware designs, the communication of hardware design and test verification
data, the maintenance, modification and procurement of hardware system.

2.1.3 ACTIVE-HDL Macro Language
All operations in Active-HDL can be performed using Active-HDL macro language. The
language has been designed to enable the user to work with Active-HDL without using the
graphical user interface (GUI).
1.HDL Editor
HDL Editor is a text editor designed for HDL source files. It displays specific syntax
categories in different colors (keyword coloring). The editor is tightly integrated with the
simulator to enable debugging source code. The keyword coloring is also available when HDL
Editor is used for editing macro files, Perl scripts, and Tcl scripts.
2.Block Diagram Editor
Block Diagram Editor is a graphical tool designed to create block diagrams. The
editor automatically translates graphically designed diagrams into VHDL or Verilog code.
3. State Diagram Editor
State Diagram Editor is a graphical tool designed to edit state machine diagrams.
The editor automatically translates graphically designed diagrams into VHDL or Verilog code.
4. Waveform Editor
Waveform Editor displays the results of a simulation run as signal waveforms. It
allows you to graphically edit waveforms so as to create desired test vectors.
5. Design Browser
The Design Browser window displays the contents of the current design, that is:
 Resource files attached to the design.
 The contents of the default-working library of the design.
 The structure of the design unit selected for simulation
 VHDL, Verilog, or EDIF objects declared within a selected region of the current
design.

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Console window
The Console window is an interactive input-output text device providing entry for
Active-HDL macro language commands, macros, and scripts. All Active-HDL tools output their
messages to Console

2.1.4 Compilation
Compilation is a process of analysis of a source file. Analyzed design units contained within the
file are placed into the working library in a format understandable for the simulator. In ActiveHDL, a source file can be on of the following:
VHDL file (.vhd)
Verilog file (.v)
EDIF net list file
State diagram file (.asf)
Block diagram file (.bde)
In the case of a block or state diagram file, the compiler analyzes the intermediate
VHDL, Verilog, or EDIF file containing HDL code (or net list) generated from the diagram.A
net list is a set of statements that specifies the elements of a circuit (for example, transistors or
gates) and their interconnection.
Active-HDL provides three compilers, respectively for VHDL, Verilog, and EDIF. When
you choose a menu command or toolbar button for compilation, Active-HDL automatically
employs the compiler appropriate for the type of the source file being compiled.

2.1.5 Simulation
The purpose of simulation is to verify that the circuit works as desired.The Active-HDL
simulator provides two simulation engines.
 Event-Driven Simulation
 Cycle-Based Simulation
The simulator supports hybrid simulation – some portions of a design can be simulated in
the event-driven kernel while the others in the cycle-based kernel. Cycle-based simulation is
significantly faster than event-driven.

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Fig2.1.5: Simulation

2.2SYNTHESISTOOL
2.2.1OVERVIEW OF XILINX ISE
Integrated Software Environment (ISE) is the Xilinx design software suite. This overview
explains the general progression of a design through ISE from start to finish. ISE enables you to
start your design with any of a number of different source types, including:
 HDL (VHDL, Verilog HDL, ABEL)
 Schematic design files
 EDIF
 NGC/NGO
 State Machines
 IP Cores
From your source files, ISE enables you to quickly verify the functionality of these sources using
the integrated simulation capabilities, including ModelSim Xilinx Edition and the HDL Bencher
test bench generator. HDL sources may be synthesized using the Xilinx Synthesis Technology
(XST) as well as partner synthesis engines used standalone or integrated into ISE. The Xilinx
implementation tools continue the process into a placed and routed FPGA or fitted CPLD, and
finally produce a bit stream for your device configuration.

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2.2.2Design Entry
ISE Text Editor - The ISE Text Editor is provided in ISE for entering design code and viewing
reports.
Schematic Editor - The Engineering Capture System (ECS) is a graphical user interface (GUI)
that allows you to create, view, and edit schematics and symbols for the Design Entry step of the
Xilinx® design flow.
CORE Generator - The CORE Generator System is a design tool that delivers parameterized
cores optimized for Xilinx FPGAs ranging in complexity from simple arithmetic operators such
as adders, to system-level building blocks such as filters, transforms, FIFOs, and memories.
Constraints Editor - The Constraints Editor allows you to create and modify the most
commonly used timing constraints.
PACE - The Pin out and Area Constraints Editor (PACE) allows you to view and edit I/O,
Global logic, and Area Group constraints.State CAD State Machine Editor - State CAD allows
you to specify states, transitions, and actions in a graphical editor. The state machine will be
created in HDL.

2.2.3 Implementation
 Translate - The Translate process runs NGD Build to merge all of the input net lists as well as
design constraint information into a Xilinx database file. Map - The Map program maps a
logical design to a Xilinx FPGA.
 Place and Route (PAR) - The PAR program accepts the mapped design, places and routes the
FPGA, and produces output for the bit stream generator.
 Floor planner - The Floor planner allows you to view a graphical representation of the FPGA,
and to view and modify the placed design.
 FPGA Editor - The FPGA Editor allows you view and modify the physical implementation,
including routing.
 Timing Analyzer - The Timing Analyzer provides a way to perform static timing analysis on
FPGA and CPLD designs. With Timing Analyzer, analysis can be performed immediately after
mapping, placing or routing an FPGA design, and after fitting and routing a CPLD design.

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 Fit (CPLD only) - The CPLDFit process maps a net list(s) into specified devices and creates
the JEDEC programming file.Chip Viewer (CPLD only) - The Chip Viewer tool provides a
graphical view of the inputs and outputs, macro cell details, equations, and pin assignments.

2.2.4 Device Download and Program File Formatting
 BitGen - The BitGen program receives the placed and routed design and produces a bit stream
for Xilinx device configuration.
 IMPACT - The iMPACT tool generates various programming file formats, and subsequently
allows you to configure your device.
 XPower - XPower enables you to interactively and automatically analyze power consumption
for Xilinx FPGA and CPLD devices.
 Integration with ChipScope Pro.

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CHAPTER 3
INTRODUCTION TO WIFI
3.1 INTRODUCTION
Wi-Fi is a popular technology that allows an electronic device to exchange
data wirelessly (using radio waves) over a computer network, including highspeed Internet connections. The Wi-Fi Alliance defines Wi-Fi as any "wireless
local area network (WLAN) products that are based on the Institute of Electri
cal and Electronics Engineers' (IEEE) 802.11 standards". However, since most
modern WLANs are based on these standards, the term "Wi-Fi" is used in general English as a
synonym for "WLAN".
A device that can use Wi-Fi (such as a personal computer, video game
console, smartphone, tablet, or digital audio player) can connect to a network resource such as
the Internet via a wireless network access point. Such an access point (or hotspot) has a range of
about 20 meters (65 feet) indoors and a greater range outdoors. Hotspot coverage can comprise
an area as small as a single room with walls that block radio waves or as large as many square
miles this is achieved by using multiple overlapping access points.
"Wi-Fi" is a trademark of the Wi-Fi Alliance and the brand name for products using
the IEEE 802.11 family of standards. Only Wi-Fi products that complete Wi-Fi
Alliance interoperability certification testing successfully may use the "Wi-Fi CERTIFIED"
designation and trademark.
Wi-Fi has had a checkered security history. Its earliest encryption system, WEP, proved
easy to break. Much higher quality protocols, WPA and WPA2, were added later. However, an
optional feature added in 2007, called Wi-Fi Protected Setup (WPS), has a flaw that allows a
remote attacker to recover the router's WPA or WPA2 password in a few hours on most
implementations. Some manufacturers have recommended turning off the WPS feature. The WiFi Alliance has since updated its test plan and certification program to ensure all newly-certified
devices resist brute-force AP PIN attacks.

1.Internet access
A Wi-Fi-enabled device can connect to the Internet when within range of a wireless
network connected to the Internet. The coverage of one or more (interconnected) access points

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called hotspots comprises an area as small as a few rooms or as large as many square miles.
Coverage in the larger area may depend on a group of access points with overlapping coverage.
Outdoor public Wi-Fi technology has been used successfully in wireless mesh networks in
London, UK.
Wi-Fi provides service in private homes, high street chains and independent businesses,
as well as in public spaces at Wi-Fi hotspots set up either free-of-charge or commercially.
Organizations and businesses, such as airports, hotels, and restaurants, often provide free-use
hotspots to attract customers. Enthusiasts or authorities who wish to provide services or even to
promote business in selected areas sometimes provide free Wi-Fi access.

2.Advantages
Wi-Fi allows cheaper deployment of local area networks (LANs). Also spaces where
cables cannot be run, such as outdoor areas and historical buildings, can host wireless LANs.
Manufacturers are building wireless network adapters into most laptops. The price of chipsets for
Wi-Fi continues to drop, making it an economical networking option included in even more
devices
Different competitive brands of access points and client network-interfaces can inter-operate at a
basic level of service.
Limitations
Spectrum assignments and operational limitations are not consistent worldwide: most of
Europe allows for an additional two channels beyond those permitted in the US for the 2.4 GHz
band (1–13 vs. 1–11), while Japan has one more on top of that (1–14). Europe, as of 2007, was
essentially homogeneous in this respect.
A Wi-Fi signal occupies five channels in the 2.4 GHz band; any two channels whose
channel numbers differ by five or more, such as 2 and 7, do not overlap. The oft-repeated adage
that channels 1, 6, and 11 are the only non-overlapping channels is, therefore, not accurate;
channels 1, 6, and 11 are the only group of three non-overlapping channels in the U.S.
EIRP in the EU is limited to 20dbm (100 mW).
The current 'fastest' norm, 802.11n, uses double the radio spectrum compared to 802.11a
or 802.11g. This means there can only be one 802.11n network on 2.4 GHz band without
interference to other WLAN traffic.

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1.Range
Wi-Fi networks have limited range. A typical wireless access point using 802.11b
or 802.11g with a stock antenna might have a range of 32 m (120 ft) indoors and 95 m (300 ft)
outdoors IEEE802.11n, however, can exceed that range by more than two times. Range also
varies with frequency band. Wi-Fi in the 2.4 GHz frequency block has slightly better range than
Wi-Fi in the 5 GHz frequency block which is used by 802.11a. On wireless routers with
detachable antennas, it is possible to improve range by fitting upgraded antennas which have
higher gain in particular directions. Outdoor ranges can be improved to many kilometers through
the use of high gain directional antennas at the router and remote device(s). In general, the
maximum amount of power that a Wi-Fi device can transmit is limited by local regulations, such
as FCC part 15 in the US.

3.2 INTRODUCTION TO WIMAX
A WiMAX system consists of two parts:
 A WiMAX tower, similar in concept to a cell-phone tower - A single WiMAX (~8,000
square km).
 A WiMAX receiver - The receiver and antenna could be a small box or PCMCIA card, or
they could be built into a laptop the way WiFi access is today.
A WiMAX tower station can connect directly to the Internet using a high-bandwidth,
wired connection (for example, a T3 line). It can also connect to another WiMAX tower using a
line-of-sight, microwave link. This connection to a second tower (often referred to as a
backhaul), along with the ability of a single tower to cover up to 3,000 square miles, is what
allows WiMAX to provide coverage to remote rural areas.

3.2.1 Block Diagram

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Fig: 3.2.1 transmission network
What this points out is that WiMAX actually can provide two forms of wireless service
 There is the non-line-of-sight, WiFi sort of service, where a small antenna on your
computer connects to the tower. In this mode, WiMAX uses a lower frequency range -2 GHz to 11 GHz (similar to WiFi). Lower-wavelength transmissions are not as easily
disrupted by physical obstructions -- they are better able to diffract, or bend, around
obstacles.
 There is line-of-sight service, where a fixed dish antenna points straight at the WiMAX
tower from a rooftop or pole. The line-of-sight connection is stronger and more stable, so
it's able to send a lot of data with fewer errors. Line-of-sight transmissions use higher
frequencies, with ranges reaching a possible 66 GHz. At higher frequencies, there is less
interference and lots more bandwidth.
 WiFi-style access will be limited to a 4-to-6 mile radius (perhaps 25 square miles or 65
square km of coverage, which is similar in range to a cell-phone zone). Through the
stronger line-of-sight antennas, the WiMAX transmitting station would send data to
WiMAX-enabled computers or routers set up within the transmitter's 30-mile radius

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(2,800 square miles or 9,300 square km of coverage). This is what allows WiMAX to
achieve its maximum range.

3.2.2 Global Area Network
The final step in the area network scale is the global area network (GAN). The proposal
for GAN is IEEE 802.20. A true GAN would work a lot like today's cell phone networks, with
users able to travel across the country and still have access to the network the whole time. This
network would have enough bandwidth to offer Internet access comparable to cable modem
service, but it would be accessible to mobile, always-connected devices like laptops or nextgeneration cell phones.
Intel will start making their Centrino laptop processors WiMAX enabled in the next two
to three years. This will go a long way toward making WiMAX a success. If everyone's laptop
already has it (which is predicted by 2008), it will be much less risky for companies to set up
WiMAX base stations.

3.2.3 WHAT CAN WIMAX DO
Intel also announced that it would be partnering with a company called

Clearwire

to

push WiMAX even further ahead. Clearwire plans to send data from WiMAX base stations to
small wireless modems. See Intel,Clearwire to Accelerate Deployment of WiMAX Networks
Worldwide (Oct. 25, 2004).
WiMAX operates on the same general principles as WiFi -- it sends data from one
computer to another via radio signals. A computer (either a desktop or a laptop) equipped with
WiMAX would receive data from the WiMAX transmitting station, probably using encrypted
data keys to prevent unauthorized users from stealing access.
The fastest WiFi connection can transmit up to 54 megabits per second under optimal
conditions. WiMAX should be able to handle up to 70 megabits per second. Even once that 70
megabits is split up between several dozen businesses or a few hundred home users, it will
provide at least the equivalent of cable-modem transfer rates to each user.
The biggest difference isn't speed; it's distance. WiMAX outdistances WiFi by miles.
WiFi's range is about 100 feet (30 m). WiMAX will blanket a radius of 30 miles (50 km) with
wireless access. The increased range is due to the frequencies used and the power of the
transmitter. Of course, at that distance, terrain, weather and large buildings will act to reduce the

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maximum range in some circumstances, but the potential is there to cover huge tracts of land.
IEEE 802.16 SpecificationsRange - 30-mile (50-km) radius from base station
 Speed - 70 megabits per second Line-of-sight not needed between user and base
station
 Frequency bands - 2 to 11 GHz and 10 to 66 GHz (licensed and unlicensed bands)
Defines both the MAC and PHY layers and allows multiple PHY-layer specifications (See How
OSI Works) WiMAX Could Boost Government Security
 In an emergency, communication is crucial for government officials as they try to
determine the cause of the problem, find out who may be injured and coordinate rescue
efforts or cleanup operations. A gas-line explosion or terrorist attack could sever the
cables that connect leaders and officials with their vital information networks.
 WiMAX could be used to set up a back-up (or even primary) communications system
that would be difficult to destroy with a single, pinpoint attack. A cluster of WiMAX
transmitters would be set up in range of a key command center but as far from each other
as possible. Each transmitter would be in a bunker hardened against bombs

3.2.4 INTRODUCTION TO DATALINK LAYER
The data link layer is layer 2 of the seven-layer OSI model of computer networking. It
corresponds to, or is part of the link layer of the TCP/IP reference model.
The data link layer is the protocol layer that transfers data between adjacent network nodes in
a wide area networkor between nodes on the same local area network segment.[1] The data link
layer provides the functional and procedural means to transfer data between network entities and
might provide the means to detect and possibly correct errors that may occur in the physical
layer. Examples of data link protocols are Ethernet for local area networks (multi-node),
the Point-to-Point

Protocol (PPP), HDLC and ADCCP for

point-to-point

(dual-node)

connections.The data link layer is concerned with local delivery of frames between devices on
the same LAN. Data-link frames, as these protocol data units are called, do not cross the
boundaries of a local network. Inter-network routing and global addressing are higher layer
functions, allowing data-link protocols to focus on local delivery, addressing, and media
arbitration. In this way, the data link layer is analogous to a neighborhood traffic cop; it
endeavors to arbitrate between parties contending for access to a medium.

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When devices attempt to use a medium simultaneously, frame collisions occur. Data-link
protocols specify how devices detect and recover from such collisions, and may provide
mechanisms to reduce or prevent them.
Delivery of frames by layer-2 devices is effected through the use of unambiguous
hardware addresses. A frame's header contains source and destination addresses that indicate
which device originated the frame and which device is expected to receive and process it. In
contrast to the hierarchical and routable addresses of the network layer, layer-2 addresses are flat,
meaning that no part of the address can be used to identify the logical or physical group to which
the address belongs.
The data link thus provides data transfer across the physical link. That transfer can be
reliable or unreliable; many data-link protocols do not have acknowledgments of
successful frame reception and acceptance, and some data-link protocols might not even have
any form of checksum to check for transmission errors. In those cases, higher-level protocols
must provide flow control, error checking, and acknowledgments and retransmission.
In some networks, such as IEEE 802 local area networks, the data link layer is described
in more detail with media access control (MAC) and logical link control (LLC) sublayers; this
means that the IEEE 802.2 LLC protocol can be used with all of the IEEE 802 MAC layers, such
as Ethernet, token ring, IEEE 802.11, etc., as well as with some non-802 MAC layers such
as FDDI. Other data-link-layer protocols, such asHDLC, are specified to include both sublayers,
although some other protocols, such as Cisco HDLC, use HDLC's low-level framing as a MAC
layer in combination with a different LLC layer. In the ITU-T G.hn standard, which provides a
way to create a high-speed (up to 1 Gigabit/s)Local area network using existing home wiring
(power lines, phone lines and coaxial cables), the data link layer is divided into three sub-layers
(application protocol convergence, logical link control and medium access control).Within the
semantics of the OSI network architecture, the data-link-layer protocols respond toservice
requests from the network layer and they perform their function by issuing service requests to
the physical layer.
 Sub layers of the data link layer
 Logical link control sub layer
 Media access control sub layer

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List of data-link-layer services
 Encapsulation of network layer data packets into frames
 Frame synchronization
 Logical link control (LLC) sublayer
Error control (automatic repeat request,ARQ), in addition to ARQ provided by
some transport-layer protocols, to forward error correction (FEC) techniques provided on
the physical layer, and to error-detection and packet canceling provided at all layers, including
the network layer. Data-link-layer error control (i.e. retransmission of erroneous packets) is
provided in wireless networks andV.42 telephone network modems, but not in LAN protocols
such as Ethernet, since bit errors are so uncommon in short wires. In that case, only error
detection and canceling of erroneous packets are provided.Flow control, in addition to the one
provided on the transport layer. Data-link-layer error control is not used in LAN protocols such
as Ethernet, but in modems and wireless networks.


Media access control (MAC) sublayer:



Multiple access protocols for channel

access control,for example CSMA/CD protocols

for collision detection and retransmission inEthernet bus networks and hub networks, or
the CSMA/CA protocol for collision avoidance in wireless networks.
Physical addressing (MAC addressing)


LAN switching (packet switching) including MAC filtering and spanning tree protocol



Data packet queueing or scheduling



Store-and-forward switching or cut-through switching



Quality of Service (QoS) control



Virtual LANs (VLAN)
The MAC sublayer is primarily concerned withrecognising where frames begin and end
in the bit-stream received from the physical layer (when receiving) delimiting the frames (when
sending), i.e. inserting information (e.g. some extra bits) into or among the frames being sent so
that the receiver(s) are able to recognise the beginning and end of the frames detection of
transmission errors by means of e.g. inserting a checksum into every frame sent and recalculating
and comparing them on the receiver side

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20



WI-FI TECHNOLOGY
inserting the source and destination MAC addresses into every frame transmitted
filtering out the frames intended for the station by verifying the destination address in the
received frames



the control of access to the physical transmission medium (i.e. which of the stations
attached to the wire or frequency range has the right to transmit?)

wimax datalink layer
Metropolitan Area Networks or (MANs) are large computer networks usually spanning
a campus or a city. They typically use wireless infrastructure or optical fiber connections to link
their sites.For instance a university or college may have a MAN that joins together many of their
local area networks (LANs) situated around site of a fraction of a square kilometer. Then from
their MAN they could have several wide area network (WAN) links to other universities or the
Internet. Some technologies used for this purpose are ATM, FDDI and SMDS. These older
technologies are in the process of being displaced by Ethernet-based MANs (e.g. Metro
Ethernet) in most areas. MAN links between LANs have been built without cables using either
microwave, radio, or infra-red free-space optical communication links.
WiMAX is a wireless metropolitan area network (MAN) technology that can connect
IEEE 802.11 (Wi-Fi) hotspots with each other and to other parts of the Internet and provide a
wireless alternative to cable and DSL for last mile (last km) broadband access. IEEE 802.16
provides up to 50 km (31 miles) of linear service area range and allows connectivity between
users without a direct line of sight. Note that this should not be taken to mean that users 50 km
(31 miles) away without line of sight will have connectivity. Practical limits from real world tests
seem to be around "3 to 5 miles" (5 to8 kilometers). The technology has been claimed to provide
shared data rates up to 70 Mbit/s, which, according to WiMAX proponents, is enough bandwidth
to simultaneously support more than 60 businesses with T1-type connectivity and well over a
thousand homes at 1Mbit/s DSL-level connectivity. Real world tests, however, show practical
maximum data rates between 500kbit/s and 2 Mbit/s, depending on conditions at a given site.
It is also anticipated that WiMAX will allow interpenetration for broadband service
provision of VoIP, video, and Internet access—simultaneously. Most cable and traditional
telephone companies are closely examining or actively trial-testing the potential of WiMAX for
"last mile" connectivity. This should result in better pricepoints for both home and business
customers as competition results from the elimination of the "captive" customer bases both

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WI-FI TECHNOLOGY
telephone and cable networks traditionally enjoyed. Even in areas without preexisting physical
cable or telephone networks, WiMAX could allow access between anyone within range of each
other. Home units the size of a paperback book that provide both phone and network connection
points are already available and easy to install.
There is also interesting potential for interoperability of WiMAX with legacy cellular
networks. WiMAX antennas can "share" a cell tower without compromising the function of
cellular arrays already in place. Companies that already lease cell sites in widespread service
areas have a unique opportunity to diversify, and often already have the necessary spectrum
available to them (i.e. they own the licenses for radio frequencies important to increased speed
and/or range of a WiMAX connection). WiMAX antennae may be even connected to an Internet
backbone via either a light fiber optics cable or a directional microwave link. Some cellular
companies are evaluating WiMAX as a means of increasing bandwidth for a variety of dataintensive applications. In line with these possible applications is the technology's ability to serve
as a very high bandwidth "backhaul" for Internet or cellular phone traffic from remote areas back
to a backbone. Although the cost-effectiveness of WiMAX in a remote application will be
higher, it is definitely not limited to such applications, and may in fact be an answer to expensive
urban deployments of T1 backhauls as well. Given developing countries' (such as in Africa)
limited wired infrastructure, the costs to install a WiMAX station in conjunction with an existing
cellular tower or even as a solitary hub will be diminutive in comparison to developing a wired
solution. The wide, flat expanses and low population density of such an area lends itself well to
WiMAX and its current diametrical range of 30 miles. For countries that have skipped wired
infrastructure as a result of inhibitive costs and unsympathetic geography, WiMAX can enhance
wireless infrastructure in an inexpensive, decentralized, deployment-friendly and effective
manner

Wimax mac layer
The IEEE 802.16 BWA network standard applies the so-called Open Systems
Interconnection (OSI) network reference seven-layer model, also called the OSI seven-layer
model. This model is very often used to describe the different aspects of a network technology. It
starts from the Application Layer, or Layer 7, on the top and ends with the PHYsical (PHY)
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WI-FI TECHNOLOGY
Layer,(or)Layer1.
The OSI model separates the functions of different protocols into a series of layers, each layer
using only the functions of the layer below and exporting data to the layer above. For example,
the IP (Internet Protocol) is in Layer 3, or the Routing Layer. Typically, only the lower layers are
implemented in hardware while the higher layers are implemented in software.The two lowest
layers are then the Physical (PHY) Layer, or Layer 1, and the Data Link Layer, or Layer 2. IEEE
802 splits the OSI Data Link Layer into two sublayers named Logical Link Control (LLC) and
Media Access Control (MAC). The PHY layer creates the physical connection between the two
communicating entities (the peer entities), while the MAC layer is responsible for the
establishment and maintenance of the connection (multiple access, scheduling, etc.).
The IEEE 802.16 standard specifies the air interface of a fixed BWA system supporting
multimedia services. The Medium Access Control (MAC) Layer supports a primarily point-tomultipoint (PMP) architecture, with an optional mesh topology. The MAC Layer is structured to
support many physical layers (PHY) specifi ed in the same standard. In fact, only two of them
The protocol layers architecture defined in WiMAX/802.16 is shown in figure . It can be seen
that the 802.16 standard defines only the two lowest layers, the PHYsical Layer and the MAC
Layer, which is the main part of the Data Link Layer, with the LLC layer very often applying the
IEEE 802.2 standard. The MAC layer is itself made of three sub-layers, the CS (Convergence
Sublayer), the CPS (Common Part Sublayer) and the Security Sublayer. The dialogue between
corresponding protocol layers or entities is made as follows. A Layer X addresses an XPDU
(Layer X Protocol Data Unit) to a corresponding Layer X (Layer X of the peer entity). This
XPDU is received as an (X.

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23

WI-FI TECHNOLOGY

CHAPTER 4
4. ARCHITECTURE AND MODULES
4.1 ARCHITECTURE

Fig 4.1 ARCHITECTURE

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24

WI-FI TECHNOLOGY

4.2MODULES
4.2.1 FIFO8X8

Fig 4.2.1 FIFO8X8
I/O Ports Description
S.N0 Port Name
1
Wr,Clk,Rd,
2
3
4
5
6
7
8
9

Rst
FIFO Ena
Data
FIFO Wr
FIFO Rd
Dout
Full
Empty

Mode Size
In
-

Port Description
Entity function synchronized for Rising edge

In

-

of the Write Clk and read Clk.
When asserted Entity is initiliased to default

In
In
In
In
Out
Out
Out

values
Enables of FIFO
[7:0] 8 bit data which input to FIFO
Write request signal of memory
Read request signal of memory
[7:0] 8 bit data which is output from FIFO
Signal Status of memory is full
Signal Status of memory is ready to read.

Functional Description
FIFO [First in First Out] is a memory that stores information. An information can be
either written into memory or read from memory. Here, we are using a 8X8 bit memory.

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25

WI-FI TECHNOLOGY
The depth of the memory is 8 bit [i.e; number of locations] and width of memory is 4 bit. Let’s,
explain this with an example when, uses it according to her requirement. In the similar fashion
the FIFO works, where we store incoming 8bit data in a memory, But to store data in a specific
location we are using write pointer as well as read pointer. These are nothing but house address.
The process consists of two parts, one is write logic and other is read logic. The process starts in
this way, When reset is inserted then the internal register i.e, Wrptr or Rdptr is cleared. Then for
every rising edge of clk whenever fifo enable is one, fifowr and fiford are one and zero
respectively, then we process the right logic. Where data is written into memory and wrptr is
incremented parallel. When fifowr and fiford are zero and one respectively, we read the data
from memory to output (Dout) using read pointer that specifies the location.
But as memory is fixed, more and more data comes that leads to overlap of existing data.
In order to avoid this problem we are using FULL and EMPTY signal, where full shows high
when memory is full by which we stop writing the data to begin reading the data from memory.
In the same way empty signal tells whether memory is empty or not, by which we begin reading
the data from memory.

SIMULATION RESULTS
SYNTHESIS REPORT
Final Report
Final Results
RTL Top Level Output File Name

fifo8x8.ngr

Top Level Output File Name

fifo8x8

Output Format

NGC

Optimization Goal

Speed

Keep Hierarchy

NO

Design Statistics
# IOs

23

Macro Statistics
# Registers

12

#

1-bit register

1

#

3-bit register

2

#

8-bit register

9

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26

WI-FI TECHNOLOGY
#

Multiplexers

7

#

2-to-1 multiplexer

4

#

8-bit 8-to-1 multiplexer

3

#

Tristates

1

#

8-bit tristate buffer

1

#

Adders/Subtractors

1

#

3-bit subtractor

1

Cell Usage
#

BELS

212

#

LUT1

4

#

LUT2

5

#

LUT3

4

#

LUT3_D

9

#

LUT3_L

104

#

LUT4

6

#

LUT4_L

2

#

MUXCY

2

#

MUXF5

48

#

MUXF6

24

#

VCC

1

#

XORCY

3

#

FlipFlops/Latches

93

#

FDCE

13

#

FDE

80

#

Clock Buffers

2

#

BUFGP

2

#

IO Buffers

21

#

IBUF

11

#

OBUF

2

#

OBUFT

8

Device utilization summary
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27

WI-FI TECHNOLOGY

Selected Device 2s15cs144-6
Number of Slices

107 out of

192

55%

Number of Slice Flip Flops

93 out of

384

24%

Number of 4 input LUTs

134 out of

384

Number of bonded IOBs

21 out of

90

Number of GCLKs

2 out of

4

34%
23%

50%

Timing Summary
Speed Grade: -6
Minimum period: 7.437ns (Maximum Frequency: 134.463MHz)
Minimum input arrival time before clock: 7.161ns
Maximum output required time after clock: 12.871ns
Maximum combinational path delay: No path found
Total memory usage is 55024 kilobytes

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WI-FI TECHNOLOGY

FLOOR PLANING

Fig 4.2.1 FLOOR PLANING

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29

WI-FI TECHNOLOGY

4.2.2 DATAMUX

Fig 4.2.2 DATAMUX
s.no
1
2
3
4
5
6

Port name
CRCOUT
DOUT
HEDAER
HECOUT
SEL
Data

Mode
Input
Input
Input
Input
Input
Output

Size
[0:7]
[0:7]
[0:7]
[0:7]
[0:1]
[0:7]

Port description
8 bit input signal
8bit input signal
8 bit input signal
8 bit input signal
Input select signal
Output data signal


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30

WI-FI TECHNOLOGY
A multiplexer has n control lines (or select lines) that select which one of 2n inputs is



transferred to the single output

SIMULATION RESULTS
SYNTHESIS REPORT
Final Report
Final Results

Mux4x1.ngr


Mux4x1

Output Format

NGC

Optimization Goal

Speed

Keep Hierarchy

NO

Design Statistics
# IOs

42

Macro Statistics
# Multiplexers
#

8-bit 4-to-1 multiplexer

1
1

Cell Usage
#

BELS

24

#

LUT3

16

#

MUXF5

8

#

IO Buffers

42

#

IBUF

34

#

OBUF

8

Selected Device

2v40cs144-4

Number of Slices

8 out of


16 out of

512

3%


42 out of

88

47%

Page
31

256

3%

WI-FI TECHNOLOGY

===============================
TIMING REPORT
NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
GENERATED AFTER PLACE-and-ROUTE.
Clock Information:
-----------------No clock signals found in this design
Timing Summary:
--------------Speed Grade

-4

Minimum period No path found
Minimum input arrival time before clock

No path found

Maximum output required time after clock

No path found

Maximum combinational path delay

7.579ns

Timing Detail:
-------------All values displayed in nanoseconds (ns)
------------------------------------------------------------------------Timing constraint

Default path analysis

Delay

7.579ns (Levels of Logic = 4)

Source

sel<0> (PAD)

Destination

Data<7> (PAD)

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32

WI-FI TECHNOLOGY
Data Path

sel<0> to Data<7>
Gate

Cell:in->out

Net

fanout Delay Delay Logical Name (Net Name)

---------------------------------------- -----------IBUF
LUT3

I->O
I0->O

MUXF5 I0->O
OBUF

I->O

16

0.825 1.000 sel_0_IBUF (sel_0_IBUF)

1 0.439 0.000 Mmux_Data_inst_lut3_21 (Mmux_Data__net3)
1 0.436 0.517 Mmux_Data_inst_mux_f5_1 (Data_1_OBUF)
4.361

Data_1_OBUF (Data<1>)

---------------------------------------Total

7.579ns (6.061ns logic, 1.518ns route)
(80.0% logic, 20.0% route)

CPU : 1.19 / 1.42 s | Elapsed : 1.00 / 1.00 s
-->

FLOOR PLANING

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33

WI-FI TECHNOLOGY

4.2.3 PARLLEL TO SERIAL

Fig 4.2.3 P TO S
s.no
1
2
3
4
5
6
7

Port name
SerEna
Clk
Data_in
Rst
Sout
SerLd
SerOvr

Mode
Input
Input
Input
Input
Out
Input
Out

Size
1 bit
[7:0]
1 bit
-

Port description
Input select signal
Input system clock signal
Input data signal
On board reset signal
Output signal
Input signal
Output Signal

This is used to convert the data from parallel form to serial form. Here it is used to satisfy the
basic requirement of the vlsi technology (i.e) utilization of less power and area with high speed.
When bits are delivered to the system serially the power and area utilization reduces and speed of
operation increases. Hence parallel to serial converter is incorporated in this project to deliver
serialized data to the system .

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34

WI-FI TECHNOLOGY

SIMULATION RESULTS
SYNTHESIS REPORT

*

Final Report

*

=====================================================================
====
Final Results

PtoS.ngr


PtoS

Output Format

NGC

Optimization Goal

Speed

Keep Hierarchy

NO

Design Statistics
#

IOs

14

Macro Statistics
#

Registers

4

#

1-bit register

2

#

3-bit register

1

#

8-bit register

1

#

Multiplexers

2

#

2-to-1 multiplexer

2

#

Tristates

1

#

1-bit tristate buffer

1

Cell Usage
#

BELS

16

#

LUT1

2

#

LUT2

3

#

LUT2_L

1

#

LUT3

1
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35

WI-FI TECHNOLOGY
#

LUT3_L

8

#

LUT4_L

1

# FlipFlops/Latches

13

#

FDCE

11

#

FDE

2

# Clock Buffers

1

#

1

BUFGP

# IO Buffers

13

#

IBUF

11

#

OBUF

1

#

OBUFT

1

=====================================================================
====
--------------------------Selected Device

2v40cs144-4

Number of Slices

9 out of

256

Number of Slice Flip Flops

13 out of

512

2%


16 out of

512

3%


13 out of

88

14%

Number of GCLKs

1 out of

16

3%

6%

=====================================================================
====
TIMING REPORT

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36

WI-FI TECHNOLOGY
Clock Information
----------------------------------------------------+------------------------+-------+
Clock Signal

| Clock buffer(FF name) | Load |

-----------------------------------+------------------------+-------+
Clk

| BUFGP

| 13

|

-----------------------------------+------------------------+-------+
Timing Summary
--------------Speed Grade

-4

Minimum period

2.125ns (Maximum Frequency: 470.699MHz)

Minimum input arrival time before clock 3.367ns
Maximum output required time after clock 6.633ns
Maximum combinational path delay

No path found

Timing Detail
------------------------------------------------------------------------Timing constraint Default period analysis for Clock 'Clk'
Delay

2.125ns (Levels of Logic = 1

Source

cnt_0 (FF)

Destination

cnt_2 (FF)

Source Clock

Clk rising

Destination Clock

Clk rising

Data Path

cnt_0 to cnt_2
Gate

Net

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37

WI-FI TECHNOLOGY
Cell in->out


---------------------------------------- -----------FDCE C->Q

4 0.568 0.747 cnt_0 (cnt_0)

LUT4_L I3->LO 1 0.439 0.000 cnt_Mmux__n0001_Result<2>1 (cnt__n0001<2>)
FDCE D

0.370

cnt_2

---------------------------------------Total

(64.8% logic, 35.2% route)

------------------------------------------------------------------------Timing constraint Default OFFSET IN BEFORE for Clock 'Clk'
Offset


Source

Ld (PAD)

Destination

Dreg_6 (FF)

Destination Clock

Clk rising

Data Path

Ld to Dreg_6
Gate

Cell in->out

Net


---------------------------------------- -----------IBUF I->O

13 0.825 0.954 Ld_IBUF (Ld_IBUF)

LUT2 I1->O
FDCE CE

11 0.439 0.908 _n00081 (_n0008)
0.240

Dreg_1

---------------------------------------Total

(44.7% logic, 55.3% route)

------------------------------------------------------------------------Timing constraint Default OFFSET OUT AFTER for Clock 'Clk'
Offset
Source
Destination

cnt_0 (FF)
Sover (PAD)

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38

WI-FI TECHNOLOGY
Source Clock:

Clk rising

Data Path: cnt_0 to Sover
Gate
Cell:in->out

Net


---------------------------------------- -----------FDCE:C->Q

4 0.568 0.747 cnt_0 (cnt_0)

LUT3:I2->O

1 0.439 0.517 _n00041 (Sover_OBUF)

OBUF:I->O

4.361

Sover_OBUF (Sover)

---------------------------------------Total

(80.9% logic, 19.1% route)

=====================================================================
====
CPU : 1.08 / 1.33 s | Elapsed : 2.00 / 2.00 s
-->

Page
39

WI-FI TECHNOLOGY

FLOOR PLANING

Page
40

WI-FI TECHNOLOGY

4.2.4 CRC( LINEAR FEEDBACK SHIFT REGISTERS)

S.N0 Port Name
1
Clk

Mode Size
In
-

Port Description
Entity function synchronized for Rising edge of

2

Rst

In

-

the Clk
When asserted Entity is initiliased to default

3
4
5

Ena
Cin
Cout

In
In
OUT

[7:0]
[7,0]

values
Enables of scrambler
8 bit data which input to crc
8 bit data which output to crc

A linear feedback shift register can be formed by performing exclusive-OR on the
outputs of two or more of the flip-flops together and feeding those outputs back into the input of
one of the flip-flops. A maximal-length LFSR produces the maximum number of PRPG patterns
possible and has a pattern count equal to 2n – 1. After verifying that the LFSR result generate the
Fault grading.
Fault grading enables the customer to ensure that the test vector set supplied for the
design will catch manufacturing defects. LFSR for built-in test (BIT) of an ASIC, it should be
noted that the LFSR logic incorporated in an ASIC can also be used to drive external logic.
LFSR created some problems, these problems can be solved by a variety of techniques,
including using longer LFSRs to generate virtually every possible input, holding key control

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42

WI-FI TECHNOLOGY
signals to a fixed value during the test stage, and augmenting the patterns with hand-generated
patterns to improve fault grading. LFSR of any significant length will generate a large number of
patterns.
For example:

Figure 4.3 a diagram of a LFSR implementing division by polynomial x5+x3+x2+1

Clock
0
1
2
3
4
5
6
7
8

Input
N/A
1
1
0
0
1
1
1
0

x0
0
1
1
0
0
1
0
0
1

x1
0
0
1
1
0
0
1
0
0

x2
0
0
0
1
1
0
1
0
1

x3
0
0
0
0
1
1
1
0
1

x4
0
0
0
0
0
1
1
1
0

Table 4.1: LFSR states for LFSR described in figure 4.8 during division of P=11001110

Simulation Results
SYNTHESIS REPORT
=====================================================================
====
*

Final Report

*

Page
43

WI-FI TECHNOLOGY
=====================================================================
====
Final Results
Output Format

: CRC.ngr
: CRC

: NGC

Optimization Goal

: Speed

Keep Hierarchy

: NO

Design Statistics
# IOs

: 12

Macro Statistics :
# Registers

:8

#

:8

1-bit register

Cell Usage :
# BELS

:4

#

LUT1

:1

#

LUT2_L

:1

#

LUT3_L

:2

# FlipFlops/Latches

:8

#

FDCE

:4

#

FDPE

:4

# Clock Buffers
#

BUFGP

# IO Buffers
#

IBUF

#

OBUF

:1
:1
: 11
:3
:8

=====================================================================
====

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44

WI-FI TECHNOLOGY
Device utilization summary:
--------------------------Selected Device : 3s400pq208-4
Number of Slices:

5 out of 3584

0%

Number of Slice Flip Flops:

8 out of 7168

0%

Number of 4 input LUTs:

4 out of 7168

0%

Number of bonded IOBs:

11 out of

7%

Number of GCLKs:

1 out of

141
8

12%

=====================================================================
====
TIMING REPORT
Clock Information:
----------------------------------------------------+------------------------+-------+
Clock Signal

| Clock buffer(FF name) | Load |

-----------------------------------+------------------------+-------+
Clk

| BUFGP

|8

|

-----------------------------------+------------------------+-------+
Timing Summary:
---------------

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45

WI-FI TECHNOLOGY
Speed Grade: -4
Timing Detail:
------------------------------------------------------------------------Timing constraint: Default period analysis for Clock 'Clk'
Delay:
Source:
Destination:
Source Clock:

Dreg_7 (FF)
Dreg_0 (FF)
Clk rising

Destination Clock: Clk rising
Data Path: Dreg_7 to Dreg_0
Gate
Cell:in->out

Net


---------------------------------------- -----------FDCE:C->Q
LUT3_L:I2->LO
FDPE:D

4 0.619 0.629 Dreg_7 (Dreg_7)
1 0.720 0.000 Mxor__n0000_Result1 (_n0000)
0.502

Dreg_4

---------------------------------------Total

(74.5% logic, 25.5% route)

-------------------------------------------------------------------------

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46

WI-FI TECHNOLOGY
Timing constraint: Default OFFSET IN BEFORE for Clock 'Clk'
Offset:


Source:

Cin (PAD)

Destination:

Dreg_0 (FF)

Destination Clock: Clk rising
Data Path: Cin to Dreg_0
Gate
Cell:in->out

Net


---------------------------------------- -----------IBUF:I->O

3 1.492 0.577 Cin_IBUF (Cin_IBUF)

LUT3_L:I1->LO
FDPE:D

1 0.720 0.000 Mxor__n0000_Result1 (_n0000)
0.502

Dreg_4

---------------------------------------Total

(82.5% logic, 17.5% route)

------------------------------------------------------------------------Timing constraint: Default OFFSET OUT AFTER for Clock 'Clk'
Offset:


Source:
Destination:
Source Clock:

Dreg_7 (FF)
Cout<7> (PAD)
Clk rising

Data Path: Dreg_7 to Cout<7>
Gate
Cell:in->out

Net


---------------------------------------- -----------FDCE:C->Q
OBUF:I->O

4 0.619 0.629 Dreg_7 (Dreg_7)
5.412

Cout_7_OBUF (Cout<7>)

----------------------------------------

Page
47

WI-FI TECHNOLOGY
Total

(90.6% logic, 9.4% route)

=====================================================================
====
CPU : 1.45 / 1.73 s | Elapsed : 1.00 / 1.00 s
-->

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.
.

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4.2.5 SERIALIZER

Clk
Rstlk
SIPOEna
Sin

Serializer

Pout[7:0]

S.N0

Port Name

Mode

Size

Port Description

1
2

Clk
Rst

In
In

Entity function synchronized for Rising edge of the Clk

3
4

SIPOEna
Sin

In
In

Enable of sipo

5

Pout

Out

When asserted Entity is initiliased to default values

[7:0]


FUNCTIONAL DESCRIPTION
Entity function synchronized for Rising edge of the Clk Entity function synchronized for Rising
edge of the Clk Entity function synchronized for Rising edge of the Clk Entity function
synchronized for Rising edge of the Clk Entity function synchronized for Rising edge of the Clk
Entity function synchronized for Rising edge of the Clk Entity function synchronized for Rising
edge of the Clk.

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SIMULATION RESULT

SYNTHESIS REPORT
=====================================================================
====
*

Final Report

*

=====================================================================
====
Final Results
Output Format

: serializer.ngr
: serializer

: NGC

Optimization Goal

: Speed

Keep Hierarchy

: NO

Design Statistics
# IOs

: 21

Macro Statistics :
# Registers

: 10

#

: 10

1-bit register

Cell Usage :
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# BELS

: 26

#

LUT1

:1

#

LUT2

:3

#

LUT3

:3

#

LUT4

: 19

# FlipFlops/Latches

: 10

#

FDC

:9

#

FDE

:1

# Clock Buffers
#

:1

BUFGP

:1

# IO Buffers
#

IBUF

#

: 20
: 10

OBUF

: 10

--------------------------Selected Device : 2s15cs144-6
Number of Slices:

15 out of

192

7%


10 out of

384

2%


26 out of

384

6%


20 out of

90

22%

Number of GCLKs:

1 out of

4

25% Timing Summary:

--------------Speed Grade: -6
Minimum period: No path found

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Total memory usage is 54000 kilobytes.

TRANSLATE

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NGDBUILD Design Results Summary:
Number of errors:

0

Number of warnings: 0
Writing NGD file "txshiftregister.ngd" ...
Writing NGDBUILD log file "txshiftregister.bld"...
MAPPING
Design Summary
-------------Number of errors:

0

Number of warnings:

0

Logic Utilization:

42 out of 1,536

2%


55 out of 1,536

3%

Logic Distribution:
Number of occupied Slices:

33 out of

768

Number of Slices containing only related logic:

33 out of

Number of Slices containing unrelated logic:

0 out of

4%
33 100%
33

0%

*See NOTES below for an explanation of the effects of unrelated logic
Total Number 4 input LUTs:

57 out of 1,536

Number used as logic:

55

Number used as a route-thru:
IOB Flip Flops:
Number of GCLKs:

3%

2
16 out of

124 12%

1
1 out of

8 12%

Total equivalent gate count for design: 869

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Additional JTAG gate count for IOBs: 768
Peak Memory Usage: 65 MB
PLACE AND ROUTE
Number of External IOBs

16 out of 124

Number of LOCed External IOBs
Number of SLICELs

0 out of 16

33 out of 768

Number of BUFGMUXs

1 out of 8

Overall effort level (-ol): Standard (set by user)
Placer effort level (-pl):

Standard (set by user)

Placer cost table entry (-t): 1
Router effort level (-rl): Standard (set by user)
Writing design to file txshiftregister.ncd.
Total REAL time to Placer completion: 0 secs
Total CPU time to Placer completion: 1 secs
Generating "par" statistics.
**************************
Generating Clock Report
**************************

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12%
0%
4%
12%

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+-------------------------+----------+------+------+------------+-------------+
|

Clock Net

| Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|

+-------------------------+----------+------+------+------------+-------------+
|

Clk_BUFGP

| BUFGMUX0| No | 23 | 0.107

| 0.349

|

+-------------------------+----------+------+------+------------+-------------+

The Delay Summary Report
The SCORE FOR THIS DESIGN is: 83
The NUMBER OF SIGNALS NOT COMPLETELY ROUTED for this design is: 0
The AVERAGE CONNECTION DELAY for this design is:
The MAXIMUM PIN DELAY IS:

0.636

2.237

The AVERAGE CONNECTION DELAY on the 10 WORST NETS is: 0.970
Listing Pin Delays by value: (nsec)
d < 1.00 < d < 2.00 < d < 3.00 < d < 4.00 < d < 5.00 d >= 5.00
--------- --------- --------- --------- --------- --------177

52

2

0

0

0

Generating Pad Report.
All signals are completely routed.
Total REAL time to PAR completion: 2 secs
Total CPU time to PAR completion: 2 secs

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Placement: Completed - No errors found.
Routing: Completed - No errors found.
Writing design to file txshiftregister.ncd.
PAR done.

FLOOR PLANING

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4.2.6 SMC

FUNCTIONAL DESCRIPTION
State machine control controls all the modulesof architecture by clk,enable and rst signal
on it.whens rst is ‘0’ it is in idle state and for every rising edge of clock all modules are
enableded and controls fifo,data mux,byte striping logic ,scrambler,lanes,8b/10b encoder and
parallel to serial converter.

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SIMULATION RESULT

SYNTHESIS REPORT

====================================================================
*

Final Report

*

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====================================================================
Final Results
Output Format

: smc.ngr
: smc

: NGC

Optimization Goal

: Speed

Keep Hierarchy

: NO

Design Statistics
# IOs

: 14

Cell Usage :
# BELS

: 12

#

LUT1

:1

#

LUT2

:1

#

LUT2_L

#

LUT3

#

LUT3_L

:2

#

LUT4_L

:6

:1
:1

# FlipFlops/Latches

:6

#

FDCE

:5

#

FDPE

:1

# Clock Buffers
#

BUFGP

# IO Buffers
#

IBUF

#

OBUF

:1
:1
: 13
:5
:8

====================================================================
--------------------------Selected Device : 2s15cs144-6
Number of Slices:

6 out of

192

6 out of

3%

384

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12 out of

384

3%


13 out of

90

14%

Number of GCLKs:

1 out of

4

25%

Timing Summary:
--------------Speed Grade: -6
Total memory usage is 51952 kilobytes.

TRANSLATE
NGDBUILD Design Results Summary:
Number of errors:

0

Number of warnings: 8

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Writing NGD file "txstatemachine.ngd" ...
Writing NGDBUILD log file "txstatemachine.bld"...
MAPPING
Design Summary
-------------Number of errors:

0

Number of warnings:

0

Logic Utilization:

8 out of 1,536


1%

10 out of 1,536

1%

Logic Distribution:
Number of occupied Slices:

8 out of

768

1%

Number of Slices containing only related logic:

8 out of

8 100%

Number of Slices containing unrelated logic:

0 out of

8

0%

*See NOTES below for an explanation of the effects of unrelated logic
Total Number of 4 input LUTs:
Number of GCLKs:

10 out of 1,536
15 out of
1 out of

1%

124 12%
8 12%

Total equivalent gate count for design: 127
Additional JTAG gate count for IOBs: 720
PLACE AND ROUTE
Number of External IOBs

15 out of 124

Number of LOCed External IOBs
Number of SLICELs

12%

0 out of 15

8 out of 768

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Number of BUFGMUXs

1 out of 8

12%

Overall effort level (-ol): Standard (set by user)
Placer effort level (-pl):

Standard (set by user)

Placer cost table entry (-t): 1
Router effort level (-rl): Standard (set by user)
Generating "par" statistics.
**************************
Generating Clock Report
**************************
+-------------------------+----------+------+------+------------+-------------+
|

Clock Net

| Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|

+-------------------------+----------+------+------+------------+-------------+
|

Clk_BUFGP

| BUFGMUX0| No |

5 | 0.007

| 0.318

|

+-------------------------+----------+------+------+------------+-------------+
The Delay Summary Report
The SCORE FOR THIS DESIGN is: 72

The NUMBER OF SIGNALS NOT COMPLETELY ROUTED for this design is: 0
The AVERAGE CONNECTION DELAY for this design is:
The MAXIMUM PIN DELAY IS:

1.771

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The AVERAGE CONNECTION DELAY on the 10 WORST NETS is: 0.831
Listing Pin Delays by value: (nsec)
d < 1.00 < d < 2.00 < d < 3.00 < d < 4.00 < d < 5.00 d >= 5.00
--------- --------- --------- --------- --------- --------55

3

0

0

0

0

Generating Pad Report.
All signals are completely routed.
Total REAL time to PAR completion: 2 secs
Total CPU time to PAR completion: 2 secs
Placement: Completed - No errors found.
Routing: Completed - No errors found.
Writing design to file txstatemachine.ncd.
PAR done.
FLOOR PLANING

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CONCLUSION
•

Various individual modules of WIMAX Transmitter have been designed, verified functionally
using VHDL-simulator, synthesized by the synthesis tool, and a final net list has been created.

•

This design of the WIMAX Transmitter is capable of transmitting all token, handshake and data
packets.

•

The Functional-simulation has been successfully carried out with the results matching with the
expected ones

•

The design has been synthesized using FPGA technology from Xilinx. This design has targeted
the device familyà spartan2, deviceà xc2s30, packageà cs144 and speed gradeà -5. This
device belongs to the Virtex–E group of FPGAs from Xilinx.

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Applications
1.To provide universal internet access signal with better coverage area.
2.Faster communication among broad band and WIFI technologies
3.Used to set up back up communication system and difficult to destroy.

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Appendix-I
7.1 Bibliography

Reference books
Basic VLSI design, 3rd Edition

Douglas A. Pucknell,
Kamran Eshraghian

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J. Bhaskar

A VHDL Primer
Digital Design

Morris Mano

Data and Computer Communications

William Stalling

Computer Networks

Andrew S. Tannenbaum

Applications of specific Integrated circuits

Michael John Sebastian Smith,

Addison Wesley

7.2 Reference Websites:
www.Deeps.org
www.usb.org
www.opencores.org
www.digitalcoredesign.org
www.EFY.com

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