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HAMDARD UNIVERSITY

SUPERVISOR:
Engr. Sheeraz Arif

CO-SUPERVISOR:
Engr. Saif Hirani
MEMBER
ABEERA FATIMA
OBJECTIVE








Trainers are quite expensive and sometime does not meet
our requirement.
Very low cost.
Help our juniors and other Engineers.
Helpful for University Labs.
DESCRIPTION OF PROJECT:
Project based trainer implemented on FPGA have following modules:
1- 8 Digit Seven Segment Multiplex display
2- 2 Line LCD Interface (2x16/2x20)
3- RS-232C
4- I2C
5- DPCM /ADPCM(optional)
FPGA
Field Programmable Gate Array.
 Contain thousands of gates.
 Fine grain architecture.
 Ability to re-program.
 Can be programmed after manufacturing.
 Using Altera.

1. 8 DIGIT SEVEN SEGMENT MULTIPLEX DISPLAY:





Display digit.
Multiplexed displays are electronic displays , that is driven one at a time.
Display is continuously active.
Used in digital, electronic meters.
CIRCUIT DIAGRAM
2. 2 LINE LCD INTERFACE: (2X16/2X20)




Use to display a real time clock.
Can display status or message error on the screen without using the PC.
Display off command to reduce power consumption.
FLOW DIAGRAM:
Power On

Wait for more than 15ms
after Vcc rises to 4.6V

RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0
0
0
0
1
1
*
*
*
*

RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0
0
0
0
1
1
*
*
*
*

Wait For more than
100µs

RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0
0
0
0
1
1
N
F
*
*
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
1
I/D
S

Wait For more than
4.1ms

Initialization End
CIRCUIT DIAGRAM
3. RS-232C:





Communicate between core system and peripheral equipments.
Asynchronous protocol,
Speed 1Mbits.
Data is bipolar.
CIRCUIT DIAGRAM

TX
Rx
4. I2C:




Inter Integrated Circuit.
Used to attach low-speed peripherals to another board.
Low manufacturing cost.
Final presentation on FPGA BASED TRAINER

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Final presentation on FPGA BASED TRAINER

  • 1.
  • 2. HAMDARD UNIVERSITY SUPERVISOR: Engr. Sheeraz Arif CO-SUPERVISOR: Engr. Saif Hirani MEMBER ABEERA FATIMA
  • 3. OBJECTIVE     Trainers are quite expensive and sometime does not meet our requirement. Very low cost. Help our juniors and other Engineers. Helpful for University Labs.
  • 4. DESCRIPTION OF PROJECT: Project based trainer implemented on FPGA have following modules: 1- 8 Digit Seven Segment Multiplex display 2- 2 Line LCD Interface (2x16/2x20) 3- RS-232C 4- I2C 5- DPCM /ADPCM(optional)
  • 5. FPGA Field Programmable Gate Array.  Contain thousands of gates.  Fine grain architecture.  Ability to re-program.  Can be programmed after manufacturing.  Using Altera. 
  • 6. 1. 8 DIGIT SEVEN SEGMENT MULTIPLEX DISPLAY:     Display digit. Multiplexed displays are electronic displays , that is driven one at a time. Display is continuously active. Used in digital, electronic meters.
  • 8. 2. 2 LINE LCD INTERFACE: (2X16/2X20)    Use to display a real time clock. Can display status or message error on the screen without using the PC. Display off command to reduce power consumption.
  • 9. FLOW DIAGRAM: Power On Wait for more than 15ms after Vcc rises to 4.6V RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 1 1 * * * * RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 1 1 * * * * Wait For more than 100µs RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 1 1 N F * * 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 I/D S Wait For more than 4.1ms Initialization End
  • 11. 3. RS-232C:     Communicate between core system and peripheral equipments. Asynchronous protocol, Speed 1Mbits. Data is bipolar.
  • 13. 4. I2C:    Inter Integrated Circuit. Used to attach low-speed peripherals to another board. Low manufacturing cost.