it is project of digital clock on fpga board in verilog language

1. Digital clock implementation on FGPA
board
BY: ABHISHEK SAINKAR
AKASH NIMBALKAR
JAYESH SURYAWANSHI

2. Contents:
 Problem Statement
 Requirements
 About the implementation process
 Code
 Output

3. Problem Statement
 To implement 7 segment Digital clock on FPGA “NEXYS 4 DDR”.

4. Requirements
 Software  Hardware

5. • About the implementation process

6. Implementation details
System design consists of Top down approach. This system performs only one
function i.e. Digital clock. This function is implemented using counter module
and display module. Counter module consist of second, minute, hour counter
which are updated by internal clock signal. Internal clock signal is generated
on the completion of every counter and it will be updated by preceding
counter.

7. Code
 Inputs
1. Reset
2. Clock
 Outputs
1. Seconds
2. Minutes
3. Hours

8. • Counters
Counter for second incrementation:
if(Clk_1sec == 1'b1) begin //at the beginning of each second
seconds = seconds + 1; //increment sec
Counter for minutes incrementation:
minutes = minutes + 1;
Counter for hours incrementation:
hours = hours + 1; //increment hours ;

9. Result