This project is based on Data Path Architecture which consists of Shift register, MAC Unit, 16-Bit ALU and Tri-State Buffer. This whole architecture is implemented by using VHDL and simulated by using Modelsim.
28. Multiply-Accumulate (MAC) What is MAC ? Multiplication followed by accumulation. Where is MAC Use ? Common operation in many digital systems, particularly those highly interconnected, like digital filters, neural networks, data quantizers, etc. What are the Features of MAC ? Multiplying two values ,then adding the result to the previously accumulated value, which must then be re-stored in the registers for future accumulations and Checking for Overflow.
29. Basic MAC Unit Types of Multiplier: 1.Unsigned Multiplier 2. Signed Multiplier
30. Design Summary MAC is 8-bit A,B: 8 bit I/P Registers prod: 16 bit O/P Register 2 Control Signals :- Start and Stop Overflow Function, which might happen when the number of MAC operations is large. Signed Adder
32. Arithmetic Logic Unit It consists of arithmetic and logic unit. Arithmetic Operation : Addition Subtraction Logical Operation : And,or,not etc.. It performs the operations according to control signal given It is basic building block of microprocessor.
35. Design Summary ALU is 16-bit A,B: 16 bit i/p reg y: 16 bit o/p register Control Signal is of 4-bitIt can support up to 16 different operations. There is a separate flag register for carry and borrow, parity and sign flag. Comparator is also included in this Alu design. ALU is working on falling edge clock.
36. Design Details: Addition variable q : std_logic_vector(16 downto 0); when "0000" => q := ('0'& a) + ('0'& b); y <= q(15 downto 0); if ( q(16) = '1' ) then f(3) <= '1'; --carry flag end if; f(1) <= '0'; --Sign flag is zero Cont………
37. Cont…. Subtraction variable q : std_logic_vector(16 downto 0); when "0001" => q := ('0'& a) - ('0'& b); y <= q(15 downto 0); if ( q(16) = '1' ) then f(1) <= '1'; --sign flag end if; f(3) <= '0'; --Carry flag is zero
38. Cont… Parity and Zero flag variable p,z : std_logic; We are checking results separately for parity and zero flag for all the operations. Parity flag (even): p := y(15) xor y(14)……..…xor y(0); if ( p = '0') then f(2) <= '1'; Zero flag: z := y(15) or y(14)……..…or y(0); if (z = '0') then f(0) <= '1';
39. Cont… Comparator when "1110" => if(a>b)then y<="0000000000000100"; elsif(a<b)then y<="0000000000000010"; elsif(a=b)then y<="0000000000000001"; f(3) <= '0'; f(1) <= '0'; Here instead of extra resistor for comparator o/p, o/p resistery is used for comp o/pt to save one resister. At later stage we can use this results by using first 3 bit of o/p resister.
40. Cont… Other function when “case" => y <= a “function” b; f(3) <= '0'; f(1) <= '0'; Syntax for functions other then addition, subtraction and comparator is like above. For these functions sign flag and zero flag is always zero.
48. 1111 Reset o/p0000 Addition 0001 Subtraction 0010 AND 0011 OR 0100 NAND 0101 NOR 0110 NOT A 0111 XOR
49.
50. Shifter The shifter is used for shifting bits one position either to the left or to the right. The Shifter operations are referred to either as shifting or rotating depends on how the end bits are shifted in or out. Here Shown Simple Shifter :
52. Design Summary Word Length: 16 bit Modeling : Behavioral Modeling Used case statements and if else statements. A ‘shift_sel’ 2-bit control Signal for selecting type of shift. Functions on Falling Edge. Operations: 00 – No Operation 01 – Left shift by 8 bit 10 – Right shift by 8 bit 11 – Rotate Right by 8 bit
56. What is Control Unit The Control Unit inside the Processor is a FSM. By Stepping through a Sequence of States, it controls the operation of Datapath. Contains Next – State circuit, State Memory Register & Output Logic circuit. Control Inputs, Status Signals. Control output, Control Signal or Control Word.
59. Control Signals For Registers: Load and Clear Signals 1 bit Start signal for enable & disable the operation of MAC unit Shifter operation depend on shift_sel signal. ALU has 4 bit control signal for performing operation alu_sel. Tristate Buffer has Out_en control signal.
62. Conclusion Designed to support high-performance, repetitive, numerically intensive tasks. Ability to complete several accesses to memory in a single instruction cycle. Performance, cost, integration, ease of development, power consumption, and other factors for the application at hand. Datapath functions have become the dominant logic type in complex logic devices.
63. Applications From radar systems to consumer electronics. DSP data path synthesis for low-power applications. Application-specific function units.