Can someone please help me with the Verilog code of this problem? I\'m lost.
Thank you An FSM is defined by the following state-assigned table. Write Verilog code for this
FSM, and simulate.
Solution
find the verilog code as below:
module FSM(w,clk,state,z) //module definition and FSM is the name of module
input w,clk; //input to FSM
output z; //output to FSM
output [1:0] state //putput state 2 bit vector
reg z; //reg to store output
reg [1:0] state //reg to stote state
parameter S0 = 2\'b00 ; //parameter to define state that is y2y1
parameter S1 = 2\'b01;
parameter S2 = 2\'b10;
parameter S3 = 2\'b11;
initial begin state = S0; z=0; end //initialize state machine with state = S0 and output z=0
//next state depends on input and present state
always @(negedge clk)
case (state)
S0 : if(w==0) state = S2 // if input w = 0 next state is 10 that is S2
elseif(w==1) state = S3 //if input =1 next state is 11 that is S3
S1 : if(w==0) state = S1 // if input w = 0 next state is 01 that is S1
elseif(w==1) state = S0 //if input =1 next state is 00 that is S0
S2 : if(w==0) state = S3 // if input w = 0 next state is 11 that is S3
elseif(w==1) state = S0 //if input =1 next state is 00 that is S0
S3 : if(w==0) state = S2 // if input w = 0 next state is 10 that is S2
elseif(w==1) state = S1 //if input =1 next state is 01 that is S1
endcase
//output
alwyas @(state or w)
case (state)
S0 : if(w==0) z=0;
elseif(w==1) z=0;
S1: if(w==0) z=0;
elseif(w==1) z=0;
S2 : if(w==0) z=0;
elseif(w==1) z=0;
S2 : if(w==0) z=0;
elseif(w==1) z=0;
S2 : if(w==0) z=0;
elseif(w==1) z=0;
S3 : if(w==0) z=1;
elseif(w==1) z=1;
endcase
endmodule.
Can someone please help me with the Verilog code of this problem I.pdf
1. Can someone please help me with the Verilog code of this problem? I'm lost.
Thank you An FSM is defined by the following state-assigned table. Write Verilog code for this
FSM, and simulate.
Solution
find the verilog code as below:
module FSM(w,clk,state,z) //module definition and FSM is the name of module
input w,clk; //input to FSM
output z; //output to FSM
output [1:0] state //putput state 2 bit vector
reg z; //reg to store output
reg [1:0] state //reg to stote state
parameter S0 = 2'b00 ; //parameter to define state that is y2y1
parameter S1 = 2'b01;
parameter S2 = 2'b10;
parameter S3 = 2'b11;
initial begin state = S0; z=0; end //initialize state machine with state = S0 and output z=0
//next state depends on input and present state
always @(negedge clk)
case (state)
S0 : if(w==0) state = S2 // if input w = 0 next state is 10 that is S2
elseif(w==1) state = S3 //if input =1 next state is 11 that is S3
S1 : if(w==0) state = S1 // if input w = 0 next state is 01 that is S1
elseif(w==1) state = S0 //if input =1 next state is 00 that is S0
S2 : if(w==0) state = S3 // if input w = 0 next state is 11 that is S3
elseif(w==1) state = S0 //if input =1 next state is 00 that is S0
S3 : if(w==0) state = S2 // if input w = 0 next state is 10 that is S2
elseif(w==1) state = S1 //if input =1 next state is 01 that is S1
endcase
//output
alwyas @(state or w)
case (state)
S0 : if(w==0) z=0;
elseif(w==1) z=0;
![Can someone please help me with the Verilog code of this problem? I'm lost.
Thank you An FSM is defined by the following state-assigned table. Write Verilog code for this
FSM, and simulate.
Solution
find the verilog code as below:
module FSM(w,clk,state,z) //module definition and FSM is the name of module
input w,clk; //input to FSM
output z; //output to FSM
output [1:0] state //putput state 2 bit vector
reg z; //reg to store output
reg [1:0] state //reg to stote state
parameter S0 = 2'b00 ; //parameter to define state that is y2y1
parameter S1 = 2'b01;
parameter S2 = 2'b10;
parameter S3 = 2'b11;
initial begin state = S0; z=0; end //initialize state machine with state = S0 and output z=0
//next state depends on input and present state
always @(negedge clk)
case (state)
S0 : if(w==0) state = S2 // if input w = 0 next state is 10 that is S2
elseif(w==1) state = S3 //if input =1 next state is 11 that is S3
S1 : if(w==0) state = S1 // if input w = 0 next state is 01 that is S1
elseif(w==1) state = S0 //if input =1 next state is 00 that is S0
S2 : if(w==0) state = S3 // if input w = 0 next state is 11 that is S3
elseif(w==1) state = S0 //if input =1 next state is 00 that is S0
S3 : if(w==0) state = S2 // if input w = 0 next state is 10 that is S2
elseif(w==1) state = S1 //if input =1 next state is 01 that is S1
endcase
//output
alwyas @(state or w)
case (state)
S0 : if(w==0) z=0;
elseif(w==1) z=0;](https://image.slidesharecdn.com/cansomeonepleasehelpmewiththeverilogcodeofthisproblemi-230326083001-3d502135/85/Can-someone-please-help-me-with-the-Verilog-code-of-this-problem-I-pdf-1-320.jpg)
